# Static function vs function static

**URL:** <https://verificationacademy.com/forums/t/static-function-vs-function-static/38152>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [October 1, 2020, 3:03pm UTC](https://verificationacademy.com/forums/t/static-function-vs-function-static/38152 "2020-10-01T15:03:35Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![OmGaneshBK](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/o/90ced4/32.png) [@OmGaneshBK](https://verificationacademy.com/forums/u/OmGaneshBK)\
**Post date:** [October 1, 2020, 3:03pm UTC](https://verificationacademy.com/forums/t/static-function-vs-function-static/38152/1 "2020-10-01T15:03:35Z")

</div>

1.My question is Module inside all the function are static in nature but how the output is behaving like an automatic .Any one can help me

```verilog
module tryfact;
  // define the function
  function integer factorial (input [31:0] operand);
  begin
    if (operand >= 2)
    factorial = factorial (operand - 1) * operand;
    else
    factorial = 1;
  end
  endfunction: factorial
  // test the function
  integer result;
  initial begin
    for (int n = 0; n <= 7; n++) begin
      result = factorial(n);
      $display("%0d factorial=%0d", n, result);
    end
  end
endmodule: tryfact

```

Output :

```auto
0 factorial=1
1 factorial=1
2 factorial=1
3 factorial=1
4 factorial=1
5 factorial=1
6 factorial=1
7 factorial=1

```

---

<div class="post-metadata">

**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [October 1, 2020, 4:19pm UTC](https://verificationacademy.com/forums/t/static-function-vs-function-static/38152/2 "2020-10-01T16:19:38Z")

</div>

_In reply to [Om Ganesh B k](https://verificationacademy.com/forums/t/static-function-vs-function-static/38152):_

Please use

````tags
(https://verificationacademy.com/forums/announcements/please-format-your-code-code-and/code-tags) making your code easier to read. I have added them for you.

Your output is not the same as if you had declared the function as automatic

``` verilog
function automatic integer factorial (input [31:0] operand);

````

I get

[code]# run -all

# 0 factorial=1

# 1 factorial=1

# 2 factorial=2

# 3 factorial=6

# 4 factorial=24

# 5 factorial=120

# 6 factorial=720

# 7 factorial=5040

```auto

```