# Shortint and int is creating Difference

**URL:** <https://verificationacademy.com/forums/t/shortint-and-int-is-creating-difference/37052>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, systemverilog-datatypes\
**Created:** [January 22, 2020, 5:17am UTC](https://verificationacademy.com/forums/t/shortint-and-int-is-creating-difference/37052 "2020-01-22T05:17:02Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [January 22, 2020, 7:05am UTC](https://verificationacademy.com/forums/t/shortint-and-int-is-creating-difference/37052/2 "2020-01-22T07:05:14Z")

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_In reply to [chashy](https://verificationacademy.com/forums/t/shortint-and-int-is-creating-difference/37052):_

The difference is that you did not run enough iterations or other tools to see that there is no difference—both example do not do always produce what you seem to expect. For example

```verilog
'{'hffffffff, 'h5, 'h28, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h107} 

```

is a valid solution top the first example. You always have to plan for overflow in Verilog expressions.

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