# Sampling clocking block output

**URL:** <https://verificationacademy.com/forums/t/sampling-clocking-block-output/38486>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [December 19, 2020, 10:29am UTC](https://verificationacademy.com/forums/t/sampling-clocking-block-output/38486 "2020-12-19T10:29:04Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![mseyunni](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/9fc29f/32.png) [@mseyunni](https://verificationacademy.com/forums/u/mseyunni)\
**Post date:** [December 19, 2020, 5:29pm UTC](https://verificationacademy.com/forums/t/sampling-clocking-block-output/38486/3 "2020-12-19T17:29:51Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/sampling-clocking-block-output/38486/2):_

Thank you Dave.  
Could you elaborate on what exactly you meant by “putting or negedge reset\_n in your clocking block event does not work the way you would want.”. Sorry, I don’t think I have understood it.

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