# Report phase **URL:** \ **Category:** UVM\ **Tags:** UVM\ **Created:** [August 22, 2018, 6:18am UTC](https://verificationacademy.com/forums/t/report-phase/34898 "2018-08-22T06:18:38Z")\ **Posts on this page:** 13\ **Page:** 1
**Author:** ![keshav\_chokshi](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/k/6a8cbe/32.png) [@keshav\_chokshi](https://verificationacademy.com/forums/u/keshav_chokshi)\ **Post date:** [August 22, 2018, 6:18am UTC](https://verificationacademy.com/forums/t/report-phase/34898/1 "2018-08-22T06:18:38Z")
Hello I am running test and my question is end\_of\_elaboration phase prints the topology informaion but report phase is not working, below is my program… ```verilog virtual function void end_of_elaboration(); print(); `uvm_info(get_type_name(), "----------TEST PASS------------------", UVM_NONE) endfunction function void report_phase(uvm_phase phase); uvm_report_server svr; super.report_phase(phase); svr = uvm_report_server::get_server(); //`uvm_info(get_type_name(), "----------TEST PASS------------------", UVM_NONE) if(svr.get_severity_count(UVM_FATAL)+svr.get_severity_count(UVM_ERROR)>0) begin `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) `uvm_info(get_type_name(), "---- TEST FAIL ----", UVM_NONE) `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) end else begin `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) `uvm_info(get_type_name(), "---- TEST PASS ----", UVM_NONE) `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) end endfunction ``` ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [August 22, 2018, 7:30am UTC](https://verificationacademy.com/forums/t/report-phase/34898/2 "2018-08-22T07:30:48Z")
_In reply to [keshav\_chokshi](https://verificationacademy.com/forums/t/report-phase/34898):_ It is useless to print simulation results in the end\_of\_elaboration\_phase, because the simulation hasn’t startexd yet. Did your simulation reach the report\_phase? This will be indicated automatically in your simulation log-file. ---
**Author:** ![keshav\_chokshi](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/k/6a8cbe/32.png) [@keshav\_chokshi](https://verificationacademy.com/forums/u/keshav_chokshi)\ **Post date:** [August 22, 2018, 7:52am UTC](https://verificationacademy.com/forums/t/report-phase/34898/3 "2018-08-22T07:52:08Z")
_In reply to [chr\_sue](https://verificationacademy.com/forums/t/report-phase/34898/2):_ > _In reply to [keshav\_chokshi](https://verificationacademy.com/forums/t/report-phase/34898/2):_ > It is useless to print simulation results in the end\_of\_elaboration\_phase, because the simulation hasn’t startexd yet. > Did your simulation reach the report\_phase? This will be indicated automatically in your simulation log-file. I am new user can you tell me whare can i see simulation log file ? ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [August 22, 2018, 8:29am UTC](https://verificationacademy.com/forums/t/report-phase/34898/4 "2018-08-22T08:29:50Z")
_In reply to [keshav\_chokshi](https://verificationacademy.com/forums/t/report-phase/34898/3):_ You should see 2 things at the end of your simulation: (1) — UVM Report Summary — (2) a message like this: reporter [TEST\_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase ---
**Author:** ![letheverifguy](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/l/c68b51/32.png) [@letheverifguy](https://verificationacademy.com/forums/u/letheverifguy)\ **Post date:** [August 22, 2018, 7:00pm UTC](https://verificationacademy.com/forums/t/report-phase/34898/5 "2018-08-22T19:00:41Z")
please check if you have UVM\_MAX\_QUIT\_COUNT set, does your test have any UVM\_ERROR/FATAL ? if the test exits with UVM\_EXIT ( on FATAL or if quit count is reached ) , the report\_phase is not executed, so what you are trying to do here wont work if your test exits with UVM\_EXIT. if you want to print any information, when tests encounters UVM\_EXIT, only function to use is pre\_abort ( in uvm\_component ) ```verilog // Function: pre_abort // // This callback is executed when the message system is executing a // action. The exit action causes an immediate termination of // the simulation, but the pre_abort callback hook gives components an // opportunity to provide additional information to the user before // the termination happens. For example, a test may want to executed // the report function of a particular component even when an error // condition has happened to force a premature termination you would // write a function like: // //| function void mycomponent::pre_abort(); //| report(); //| endfunction // // The pre_abort() callback hooks are called in a bottom-up fashion. ``` or you can use final\_block in a module. ---
**Author:** ![sharatk](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/e0b2c6/32.png) [@sharatk](https://verificationacademy.com/forums/u/sharatk)\ **Post date:** [November 1, 2019, 11:51pm UTC](https://verificationacademy.com/forums/t/report-phase/34898/6 "2019-11-01T23:51:17Z")
_In reply to [sohan\_b](https://verificationacademy.com/forums/t/report-phase/34898/5):_ Would you guys know of a reason why pre\_abort isnt getting called with UVM\_TIMEOUT expires? ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [November 2, 2019, 10:07am UTC](https://verificationacademy.com/forums/t/report-phase/34898/7 "2019-11-02T10:07:19Z")
_In reply to [sharatk](https://verificationacademy.com/forums/t/report-phase/34898/6):_ When timeout expeires you might not have any UVM\_ERROR. In this case you have a tsructural problem. Your simulation might hang or it runs in an infinite loop. The question for UVM\_ERROR is not relevant in this case. Per definition pre\_abort is only execuetd on UVM\_EXIT and this depends on your parameter UVM\_MAX\_QUIT\_COUNT. ---
**Author:** ![sharatk](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/e0b2c6/32.png) [@sharatk](https://verificationacademy.com/forums/u/sharatk)\ **Post date:** [November 5, 2019, 12:16am UTC](https://verificationacademy.com/forums/t/report-phase/34898/8 "2019-11-05T00:16:59Z")
_In reply to [chr\_sue](https://verificationacademy.com/forums/t/report-phase/34898/7):_ Can you please explain. I see an infinite loop. 668195000: !e[31mUVM\_ERRORe[0m! [e[36muvm\_test\_top.env.LLC\_SCBe[0m] e[31mrdAddrQ is not emptye[0m (/project/freya/fba/design/sharatk/dv\_0/fbsource/fbcode/infra\_asic\_fpga/ip/fb\_inference/dv/fb\_inf\_llc/gen/…/env/fb\_inf\_llc\_sb\_ext.sv:1421) 668195000: [uvm\_test\_top.env.LLC\_SCB] Calling pre-abort 668195000: [uvm\_test\_top.env.LLC\_SCB] In Check-Phase 668195000: [uvm\_test\_top.env.LLC\_SCB] check\_phase rdAddrQ. Addr-a0ea92340 ID-0 LEN-1 668195000: !e[31mUVM\_ERRORe[0m! [e[36muvm\_test\_top.env.LLC\_SCBe[0m] e[31mrdAddrQ is not emptye[0m (/project/freya/fba/design/sharatk/dv\_0/fbsource/fbcode/infra\_asic\_fpga/ip/fb\_inference/dv/fb\_inf\_llc/gen/…/env/fb\_inf\_llc\_sb\_ext.sv:1421) 668195000: [uvm\_test\_top.env.LLC\_SCB] Calling pre-abort 668195000: [uvm\_test\_top.env.LLC\_SCB] In Check-Phase 668195000: [uvm\_test\_top.env.LLC\_SCB] check\_phase rdAddrQ. Addr-a0ea92340 ID-0 LEN-1 This is my function virtual function void pre\_abort(); `uvm\_info(get\_full\_name, “Calling pre-abort”, UVM\_NONE ) check\_phase(null); endfunction My quit\_coiut is set as 1. ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [November 5, 2019, 7:46am UTC](https://verificationacademy.com/forums/t/report-phase/34898/9 "2019-11-05T07:46:50Z")
_In reply to [sharatk](https://verificationacademy.com/forums/t/report-phase/34898/8):_ For the method check\_phase(): The uvm\_check\_phase phase implementation method. This method should never be called directly. Do you see the above data only twice or more than twice? ---
**Author:** ![sharatk](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/e0b2c6/32.png) [@sharatk](https://verificationacademy.com/forums/u/sharatk)\ **Post date:** [November 5, 2019, 7:54am UTC](https://verificationacademy.com/forums/t/report-phase/34898/10 "2019-11-05T07:54:13Z")
_In reply to [chr\_sue](https://verificationacademy.com/forums/t/report-phase/34898/9):_ The main reason to implement pre\_abort was if the test is being killed by UVM\_TIMEOUT, it never calls post-run phases. So thats why I put check\_phase inside pre\_abort. What I think is happening is. check\_phase generates an UVM\_ERROR. Because of max\_error\_count being 1, it exits and calls pre\_abort, which again calls check and that calls pre\_abort. If this is true , then I think its a UVM bug. ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [November 5, 2019, 8:07am UTC](https://verificationacademy.com/forums/t/report-phase/34898/11 "2019-11-05T08:07:56Z")
_In reply to [sharatk](https://verificationacademy.com/forums/t/report-phase/34898/10):_ Be careful with the bug. You did not answer my 2nd question. Could you please do it now? ---
**Author:** ![sharatk](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/e0b2c6/32.png) [@sharatk](https://verificationacademy.com/forums/u/sharatk)\ **Post date:** [November 5, 2019, 8:11am UTC](https://verificationacademy.com/forums/t/report-phase/34898/12 "2019-11-05T08:11:15Z")
_In reply to [chr\_sue](https://verificationacademy.com/forums/t/report-phase/34898/11):_ Sorry about that. The test was stuck in an infinite loop and I saw those prints a lot of times. ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [November 5, 2019, 8:34am UTC](https://verificationacademy.com/forums/t/report-phase/34898/13 "2019-11-05T08:34:38Z")
_In reply to [sharatk](https://verificationacademy.com/forums/t/report-phase/34898/12):_ OK, I bekieve you are hunting for something you could see implementing appropriate `uvm_info and `uvm\_error in your testbench code. Investigate this line of code. 668195000: ![31mUVM\_ERROR[0m! [[36muvm\_test\_top.env.LLC\_SCB[0m] [31mrdAddrQ is not empty[0m (/project/freya/fba/design/sharatk/dv\_0/fbsource/fbcode/infra\_asic\_fpga/ip/fb\_inference/dv/fb\_inf\_llc/gen/…/env/fb\_inf\_llc\_sb\_ext.sv:1421) What are you doing here?