# Register model initial values **URL:** \ **Category:** UVM\ **Tags:** uvm-register-model, UVM\ **Created:** [February 28, 2017, 2:28pm UTC](https://verificationacademy.com/forums/t/register-model-initial-values/32918 "2017-02-28T14:28:54Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![stefanotraferro](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/9fc29f/32.png) [@stefanotraferro](https://verificationacademy.com/forums/u/stefanotraferro)\ **Post date:** [February 28, 2017, 2:28pm UTC](https://verificationacademy.com/forums/t/register-model-initial-values/32918/1 "2017-02-28T14:28:54Z")
Hi, I am not a very expert UVM user and I am running some trials with the register model. In my testbench I have the following loop just to print the content of the register model: ```verilog my_regmodel.get_blocks(blks, UVM_HIER); foreach (blks[b]) begin $display("Block: %s (%s)", blks[b].get_name(), blks[b].get_full_name()); blks[b].get_registers(regs, UVM_HIER); foreach (regs[r]) begin $display("%s (%s) @0x%8h", regs[r].get_name(), regs[r].get_full_name(), regs[r].get_address()); regs[r].get_fields(fields); foreach (fields[f]) begin $display(" %s (%s): LSB=%0d, size=%0d, access=%s, reset_value=0x%0h, current_value=0x%0h", fields[f].get_name(), fields[f].get_full_name(), fields[f].get_lsb_pos(), fields[f].get_n_bits(), fields[f].get_access(), fields[f].get_reset(), fields[f].get() ); end while (fields.size() > 0) void'(fields.pop_front()); // Empty the queue end while (regs.size() > 0) void'(regs.pop_front()); // Empty the queue end while (blks.size() > 0) void'(blks.pop_front()); // Empty the queue ``` This loop executed before any physical register access is performed. I have the following question: - why for all the registers the value I’m getting (get()) is different from the reset value and always 0? (of course there are a lot of registers with reset value different from 0). Am I missing any operation to “synchronize” the model with the actual state of the circuit? Thanks a lot in advance for any help. Best regards, Stefano ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [March 2, 2017, 12:13pm UTC](https://verificationacademy.com/forums/t/register-model-initial-values/32918/2 "2017-03-02T12:13:14Z")
_In reply to [stefanotraferro](https://verificationacademy.com/forums/t/register-model-initial-values/32918):_ Hi Stefano, in which phase are you exercising your register model? ---
**Author:** ![stefanotraferro](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/9fc29f/32.png) [@stefanotraferro](https://verificationacademy.com/forums/u/stefanotraferro)\ **Post date:** [March 2, 2017, 12:45pm UTC](https://verificationacademy.com/forums/t/register-model-initial-values/32918/3 "2017-03-02T12:45:04Z")
_In reply to [chr\_sue](https://verificationacademy.com/forums/t/register-model-initial-values/32918/2):_ Hi, thanks for replying. This piece of code is in the body of my test sequence and it is executed after calling ```verilog super.body() ``` My test sequence is a derived class from a class which is, in turn, derived from uvm\_reg\_sequence: - uvm\_reg\_sequence - - my\_parent\_seq [list] - my\_seq [/list] The code of my\_parent\_seq is simply: ```verilog class my_parent_seq extends uvm_reg_sequence; `uvm_object_utils(my_parent_seq) my_reg_model regmodel; // Sequencer my_uvc_sequencer p_sequencer; function new(string name = ""); super.new(name); set_automatic_phase_objection(1); endfunction: new virtual task body(); assert($cast(p_sequencer, m_sequencer)); assert($cast(regmodel, p_sequencer.cfg.regmodel)); endtask: body endclass: my_parent_seq ``` What I’ve noticed is that the values returned by get() are updated to the actual value only after a physical read, which is not would I would expect. Here’s a practical example: - I have a register with default (reset) value 0x03fc; - the two LSBs are associated to a field; - I change the value of that field to 3: ```verilog temp_reg = my_regmodel.reg_blk.get_reg_by_name("my_region.my_reg"); temp_field = temp_reg.get_field_by_name("my_field"); temp_field.set( 3 ); temp_reg.update(status); assert(status == UVM_IS_OK); ``` At this point, I am expecting the generated transaction to write 0x03ff to the register, instead it writes 0x0003. The only way to get 0x03ff is to read the register first. Another note: the UVM test reg\_all passes I guess just for the reason that the first set of accesses is a read of the complete register map to perform the reset value sub-test. Is all of this expected? Am I really supposed to physically read the complete register map to have a consistent model? Thanks in advance for any help. ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [March 2, 2017, 2:45pm UTC](https://verificationacademy.com/forums/t/register-model-initial-values/32918/4 "2017-03-02T14:45:28Z")
_In reply to [stefanotraferro](https://verificationacademy.com/forums/t/register-model-initial-values/32918/3):_ After constructing a sequence with sequence items are data fields are initialized to its inital values. If you want to see the reste values you have to execute a reset sequence first. The UVM library provides you such a sequence (uvm\_reg\_hw\_reset\_seq). ---
**Author:** ![stefanotraferro](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/9fc29f/32.png) [@stefanotraferro](https://verificationacademy.com/forums/u/stefanotraferro)\ **Post date:** [March 2, 2017, 3:27pm UTC](https://verificationacademy.com/forums/t/register-model-initial-values/32918/5 "2017-03-02T15:27:04Z")
_In reply to [chr\_sue](https://verificationacademy.com/forums/t/register-model-initial-values/32918/4):_ Thanks for your reply. So, since uvm\_reg\_hw\_reset\_seq performs physical register accesses, the initialization of the model is done through actual register access as I was guessing, isn’t it? Am I missing something? ---
**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\ **Post date:** [March 2, 2017, 4:19pm UTC](https://verificationacademy.com/forums/t/register-model-initial-values/32918/6 "2017-03-02T16:19:50Z")
_In reply to [stefanotraferro](https://verificationacademy.com/forums/t/register-model-initial-values/32918/5):_ No it is not the initializaion it is setting the reg values to its reset value and it goes through accessing the registers physically. ---
**Author:** ![stefanotraferro](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/9fc29f/32.png) [@stefanotraferro](https://verificationacademy.com/forums/u/stefanotraferro)\ **Post date:** [March 2, 2017, 4:59pm UTC](https://verificationacademy.com/forums/t/register-model-initial-values/32918/7 "2017-03-02T16:59:55Z")
_In reply to [chr\_sue](https://verificationacademy.com/forums/t/register-model-initial-values/32918/6):_ Thanks for the reply. I guess I’ve found the solution: the .reset() method must be invoked to synchronize the mirrored values with the reset values: ```verilog my_regmodel.reset() ``` This method is called by the sequences available in the UVM library, but must be explicitly called in case of a custom sequence.