# Randomization failure with Inline constraint

**URL:** <https://verificationacademy.com/forums/t/randomization-failure-with-inline-constraint/38270>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, systemverilog-constraint, inline-constraints-handling, randomization\
**Created:** [October 27, 2020, 4:22pm UTC](https://verificationacademy.com/forums/t/randomization-failure-with-inline-constraint/38270 "2020-10-27T16:22:18Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![sj1992](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/ecae2f/32.png) [@sj1992](https://verificationacademy.com/forums/u/sj1992)\
**Post date:** [October 27, 2020, 5:39pm UTC](https://verificationacademy.com/forums/t/randomization-failure-with-inline-constraint/38270/3 "2020-10-27T17:39:11Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/randomization-failure-with-inline-constraint/38270/2):_

Hi Dave,

I made a mistake in my previous code. Here is the code

```verilog

class item;
rand unsigned int a, b,c, d;
constraint cst{
solve d before b;
solve a before c;
solve b before c;
(d==0) -> b == 40;
c == a+b;
}
constraint cst_d{
d dist{
0:=10,
1:=80
};
}
endclass
 
class some_other_class;
item.randomize with {
c < 8;
}
endclass

```

Thanks.

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