# Random assignment to queues in class

**URL:** <https://verificationacademy.com/forums/t/random-assignment-to-queues-in-class/38049>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, systemverilog-constraint\
**Created:** [September 9, 2020, 1:03am UTC](https://verificationacademy.com/forums/t/random-assignment-to-queues-in-class/38049 "2020-09-09T01:03:14Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![DhavalP](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/d/90db22/32.png) [@DhavalP](https://verificationacademy.com/forums/u/DhavalP)\
**Post date:** [September 9, 2020, 1:03am UTC](https://verificationacademy.com/forums/t/random-assignment-to-queues-in-class/38049/1 "2020-09-09T01:03:14Z")

</div>

How to assign qu given in module to three different queues(q1, q2 ,q3) in given class randomly such that equal no. of elements of qu is assigned to q1, q2 and q3? Assigned values should be unique. I have taken 15 elements in qu so q1, q2 and q3 should have 5 unique elements here.

```auto
class Base;
  rand int q1[$], q2[$], q3[$];
  
endclass

module top;
  Base base = new();
  int qu[$] = {16,1,2,3,4,5,6,7,8,9,10,11,12,13,14};
    
endmodule

```

---

<div class="post-metadata">

**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [September 9, 2020, 5:29am UTC](https://verificationacademy.com/forums/t/random-assignment-to-queues-in-class/38049/2 "2020-09-09T05:29:33Z")

</div>

_In reply to [DhavalP](https://verificationacademy.com/forums/t/random-assignment-to-queues-in-class/38049):_

```verilog
module top;
  Base base = new();
  int qu[$] = {16,1,2,3,4,5,6,7,8,9,10,11,12,13,14};
  initial begin
    assert(base.randomize() with {
      q1.size() == qu.size()/3;
      q2.size() == qu.size()/3;
      q3.size() == qu.size()/3;
      unique {q1,q2,q3};
      foreach(qu[i]) qu[i] inside {q1,q2,q3};
    } );
    $display("%p",base);
  end
endmodule

```