# Raise\_objection in uvm\_sequence class

**URL:** <https://verificationacademy.com/forums/t/raise-objection-in-uvm-sequence-class/34781>\
**Category:** UVM\
**Tags:** UVM, sequence-raise-and-drop-phase\
**Created:** [July 31, 2018, 3:01pm UTC](https://verificationacademy.com/forums/t/raise-objection-in-uvm-sequence-class/34781 "2018-07-31T15:01:08Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [July 31, 2018, 3:17pm UTC](https://verificationacademy.com/forums/t/raise-objection-in-uvm-sequence-class/34781/2 "2018-07-31T15:17:26Z")

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_In reply to [peter](https://verificationacademy.com/forums/t/raise-objection-in-uvm-sequence-class/34781):_

You do not raise and drop a phase. You are raising and dropping objections.  
This is required by the UVM. If you do not implement objections your simulation will stuck at time 0.  
ojections can be implemented in any UVM component or in a sequence.  
The recommendation is to implement as less as possible. The best and recommended way is to implement objections in the test.

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