# Question on UVM Phases

**URL:** <https://verificationacademy.com/forums/t/question-on-uvm-phases/51708>\
**Category:** UVM\
**Tags:** uvm\_phases, UVM, UVM-phases\
**Created:** [July 24, 2026, 12:17pm UTC](https://verificationacademy.com/forums/t/question-on-uvm-phases/51708 "2026-07-24T12:17:14Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![Praveen\_Kakodra](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/c77e96/32.png) [@Praveen\_Kakodra](https://verificationacademy.com/forums/u/Praveen_Kakodra)\
**Post date:** [July 24, 2026, 12:17pm UTC](https://verificationacademy.com/forums/t/question-on-uvm-phases/51708/1 "2026-07-24T12:17:14Z")

</div>

Hi,

I have my USB UVC Agent declared as

```verilog
class usb_agent #(int XCVR_SELECT_WIDTH) extends vc_agent;
   ........
// Inherits 'm_sequencer' which is of Type Parameter of parent class of vc_agent
   virtual task run_phase(uvm_phase phase);
     super.run_phase(phase);
     if( cfg.agent_cfg.is_active && cfg.agent_cfg.start_default_seq) begin
       fork
         if( cfg.agent_cfg.agent_type inside { DEV,OTG_A_DEV,OTG_B_DEV } begin
            dev_seq dev_seq_h = dev_seq::type_id::create("dev_seq");
            dev_seq.start(m_sequencer);
         end
       join
     end
   endtask
endclass

```

I noticed that there is no objection raised within run\_phase

Within class vc\_agent and it’s super classes ( which is extended uvm\_component ) I observe that there is no definition of run\_phase.

Task `run_phase` within uvm\_component calls another task `run()` which simply returns

Hence call to `super.run_phase(phase)` essentially calls `run_phase` defined in class uvm\_component **which doesn’t raise & drop an objection**

Our test class overrides the pre\_reset\_phase , reset\_phase and main\_phase where it raises and drops an objection

As run\_phase executes in parallel with sub-phases, **does the sequence started in usb\_agent’s run\_phase continue execution till the objection is dropped in test’s main\_phase ?**

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<div class="post-metadata">

**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [July 24, 2026, 1:46pm UTC](https://verificationacademy.com/forums/t/question-on-uvm-phases/51708/2 "2026-07-24T13:46:53Z")

</div>

The run\_phase() will execute in parallel with all of the other run-phases, so the dev\_seq should run during the entire run-phase of your simulation.

The differing use of phases can lead to unpredictable behavior, especially when you bring in VIP from various sources that use phases in other ways than expected. This is why it is strongly recommended to use only the run\_phase() and utilize sequences as your phasing (i.e. pre\_reset\_sequence, reset\_sequence, main\_sequence, etc.)