# Question on " read task " of uvm\_reg **URL:** \ **Category:** UVM\ **Tags:** UVM\ **Created:** [July 23, 2023, 7:24am UTC](https://verificationacademy.com/forums/t/question-on-read-task-of-uvm-reg/41987 "2023-07-23T07:24:14Z")\ **Posts on this page:** 1\ **Page:** 1
**Author:** ![user116](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/u/9fc29f/32.png) [@user116](https://verificationacademy.com/forums/u/user116)\ **Post date:** [July 23, 2023, 7:24am UTC](https://verificationacademy.com/forums/t/question-on-read-task-of-uvm-reg/41987/1 "2023-07-23T07:24:14Z")
Hello, I have a question on read task of uvm\_reg. The uvm reference manual gives following description of read task: ```verilog virtual task read(output uvm_status_e status, output uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0 ) ``` Read the current value from this register Read and return value from the DUT register that corresponds to this abstraction class instance using the specified access path. If the register is mapped in more than one address map, an address map must be specified if a physical access is used (front-door access). If a back-door access path is used, the effect of reading the register through a physical access is mimicked. For example, clear-on-read bits in the registers will be set to zero. The mirrored value will be updated using the uvm\_reg::predict() method. **Why is the argument uvm\_sequence\_base i.e. handle to parent sequence required here?** Also manual says that meaning of UVM\_DEFAULT\_PATH is **operation specified by context**. What does that mean? How is the operation specified by context? **If we supply path argument as UVM\_DEFAULT\_PATH, how does the task infer backdoor or frontdoor access?** regards, -sunil