# Question on "local variable flowing out of ORing of two sequences"

**URL:** <https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [June 7, 2023, 9:47am UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772 "2023-06-07T09:47:20Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![user116](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/u/9fc29f/32.png) [@user116](https://verificationacademy.com/forums/u/user116)\
**Post date:** [June 8, 2023, 5:58am UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/4 "2023-06-08T05:58:10Z")

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Thanks Ben for a detailed reply. I am clear about the concept now.  
I have another question - Do the sequences have parameters like parametrized classes or module parameters?

regards,  
-sunil puranik

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