# Question on "local variable flowing out of ORing of two sequences"

**URL:** <https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [June 7, 2023, 9:47am UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772 "2023-06-07T09:47:20Z")\
**Posts on this page:** 9\
**Page:** 1

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**Author:** ![user116](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/u/9fc29f/32.png) [@user116](https://verificationacademy.com/forums/u/user116)\
**Post date:** [June 7, 2023, 9:47am UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/1 "2023-06-07T09:47:20Z")

</div>

Hi,  
I have a question on the the property definition given in paper " **SVA Alternative for Complex Assertions  
by Ben Cohen, VHDL Cohen Publishing"**

```verilog

property p_check_msg_BAD2;
 BITS_4 sum;
 bit result;
 ($rose(go), sum=0) |->(
 ((vld[->1], sum=sum+data)[*999999]) or
 ($fell(go)[->1], result=check_sum_simple
 (sum, data)) )
 ##0 result; // line 22
endproperty

```

ap\_check\_msg\_BAD: assert property(p\_check\_msg\_BAD2);  
// \*\* Error: check\_sum.sv(22):  
\*\* ERROR: Local variable result  
is referenced in an expression  
where it does not flow.

I am not clear about the statement **“local variable result does not flow out of ORing of two sequences”.** Can someone explain what that means.

regards,  
-sunil

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**Author:** ![MICRO\_91](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/5f9b8f/32.png) [@MICRO\_91](https://verificationacademy.com/forums/u/MICRO_91)\
**Post date:** [June 7, 2023, 5:37pm UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/2 "2023-06-07T17:37:53Z")

</div>

_In reply to [puranik.sunil@tcs.com](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772):_

The assignment to local variable **‘result’ exists for only one of the sequence** instead of both the sequences .

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**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [June 7, 2023, 7:32pm UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/3 "2023-06-07T19:32:10Z")

</div>

On \*_((vld[-\>1], sum=sum+data)[999999])_  
the [\*999999] is not needed and does not make sense because  
the sequence\_match\_item sum=sum+data will only be activated when vld==1.  
After that, the left sequence is done.  
Consider firing a task from the squence\_match\_item. Something like the following (untested):

```verilog

default clocking @(posedge clk); endclocking
// Needed because of the $sampled
task automatic t_sum(); // data is a module signal
  BITS_4 vsum;
  // wait(vld) // no
  fork
    begin : fork_sum 
        while ($sampled(!vld) begin 
            vsum=$sampled(sum) +$sampled(data);
             @(posedge clk); 
    end : fork_sum 
    begin : vld_go 
        wait($sampled(vld) || $samled(go));
        am_result: assert(check_sum_simple(vsum, $sampled(data)));
    end :vld_go   
  join
endtask: t_sum
ap_sum: assert property($rose(go) |-> (1, t_sum())); 

```

 ![](https://verificationacademy.com/forums/uploads/default/original/1X/854d339ec416503007283f77b11d7420f047f36e.png)  
 ![](https://verificationacademy.com/forums/uploads/default/original/1X/43b15ab88e93ef7e595c8d86888e0289856374f6.png)  
 ![](https://verificationacademy.com/forums/uploads/default/original/1X/0d75a5ec3de0371067d5c0ebf7fe44b32d176b4b.png)  
 ![](https://verificationacademy.com/forums/uploads/default/original/1X/eccd359951aa41453a8de89ffd613821d21c2e74.png)

 ![](https://verificationacademy.com/forums/uploads/default/original/1X/854d339ec416503007283f77b11d7420f047f36e.png)

 ![](https://verificationacademy.com/forums/uploads/default/original/1X/43b15ab88e93ef7e595c8d86888e0289856374f6.png)

 ![](https://verificationacademy.com/forums/uploads/default/original/1X/0d75a5ec3de0371067d5c0ebf7fe44b32d176b4b.png)

 ![](https://verificationacademy.com/forums/uploads/default/original/1X/eccd359951aa41453a8de89ffd613821d21c2e74.png)

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<div class="post-metadata">

**Author:** ![user116](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/u/9fc29f/32.png) [@user116](https://verificationacademy.com/forums/u/user116)\
**Post date:** [June 8, 2023, 5:58am UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/4 "2023-06-08T05:58:10Z")

</div>

Thanks Ben for a detailed reply. I am clear about the concept now.  
I have another question - Do the sequences have parameters like parametrized classes or module parameters?

regards,  
-sunil puranik

---

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**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [June 8, 2023, 8:47am UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/5 "2023-06-08T08:47:42Z")

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_In reply to [puranik.sunil@tcs.com](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/4):_

Sequences are within modules, interfaces, checkers.  
Sequences can have arguments that can refer to the parameters.  
Ben Cohen  
[Ben@systemverilog.us](mailto:Ben@systemverilog.us)  
Link to the list of papers and books that I wrote, many are now donated.

> **[Cohen\_Links\_to\_papers\_books.pdf](https://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf)**
>
> 141.16 KB

or [Cohen\_Links\_to\_papers\_books - Google Docs](https://rb.gy/ibks5p)

Getting started with verification with SystemVerilog

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>
> Got this question: 
> Q: I need your advice in getting started with verification with systemverilog. I 've built various projects using Verilog and they was…

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**Author:** ![hisingh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/h/97f17d/32.png) [@hisingh](https://verificationacademy.com/forums/u/hisingh)\
**Post date:** [June 12, 2023, 3:27pm UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/6 "2023-06-12T15:27:35Z")

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_In reply to [ben@SystemVerilog.us](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/5):_

Hi Ben ,  
Could you please further explain the above comment :

> On ((vld[-\>1], sum=sum+data)[\*999999])  
> the [\*999999] is not needed and does not make sense because  
> the sequence\_match\_item sum=sum+data will only be activated when vld==1.  
> After that, the left sequence is done.

‘or’ operator completes as soon as the former of LHS or RHS is true.  
Let’s assume a case that $fell(go) is never true .  
**Won’t local variable sum be assigned on each occurrence of vld[-\>1] then ?**  
So the only way ‘or’ operator completes is when the LHS ( vld[-\>1] ) is true , 999999 times consecutively .  
This would mean that sum is assigned 999999 times ( using prior value of sum )

Please correct me if wrong .

Thanks ,  
hisingh

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**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [June 12, 2023, 4:07pm UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/7 "2023-06-12T16:07:33Z")

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_In reply to [hisingh](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/6):_  
( sequence\_expr {, sequence\_match\_item } ) [sequence\_abbrev]  
1800: Consecutive repetition ( [\*const\_or\_range\_expression] ): Consecutive repetition specifies finitely many iterative **matches of the operand sequence** , with a delay of one clock tick from the end of one match to the beginning of the next. The overall repetition sequence matches at the end of the last iterative match of the operand.

When the sequence\_expr is a match the sequence\_match\_item is executed.  
Thus, in (vld[-\>1], sum=sum+data )[\*3]  
when vld[-\>1] is a match (i.e., when the sequence ends with vld==1) the  
sum=sum+data is executed. You then repeat that operation 3 times.

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**Author:** ![hisingh](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/h/97f17d/32.png) [@hisingh](https://verificationacademy.com/forums/u/hisingh)\
**Post date:** [June 12, 2023, 4:17pm UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/8 "2023-06-12T16:17:04Z")

</div>

_In reply to [ben@SystemVerilog.us](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/7):_

Thanks Ben .  
So when vld[-\>1] is true for 2nd time , the previous value of sum ( assigned when vld[-\>1] was true for 1st time ) is used to calculate the new value of sum.

So had we written :

```verilog

property p_check_msg_BAD2;
 BITS_4 sum;
 bit result;
 ($rose(go), sum=0) |-> ( 
 ( ( vld[->1], sum=sum+data )[*3] ) or ( $fell(go)[->1] , sum = sum+data ) )
  ##0 ( 1 , result = check_sum_simple(sum, data) ) ##0 result; 
endproperty

```

Assuming that $fell(go) is never true , **the ‘or’ operator is true only when vld[-\>1] is true thrice ( sum is assigned thrice as well )**

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**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [June 12, 2023, 4:27pm UTC](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/9 "2023-06-12T16:27:31Z")

</div>

_In reply to [hisingh](https://verificationacademy.com/forums/t/question-on-local-variable-flowing-out-of-oring-of-two-sequences/41772/8):_

> Assuming that $fell(go) is never true , the ‘or’ operator is true only when vld[-\>1] is true thrice ( sum is assigned thrice as well )

Yes.

```verilog

 (1, sum=sum+1)[*1:99999] ##0 vld; // sum==0 initially
// if vld=1 after 100 cycles, sum==100 

```