# Put a transaction into analysis fifo

**URL:** <https://verificationacademy.com/forums/t/put-a-transaction-into-analysis-fifo/42786>\
**Category:** UVM\
**Tags:** UVM, UVM-UVM\_TLM\_ANALYSIS\_FIFO\
**Created:** [December 3, 2023, 12:33pm UTC](https://verificationacademy.com/forums/t/put-a-transaction-into-analysis-fifo/42786 "2023-12-03T12:33:15Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [December 6, 2023, 2:02pm UTC](https://verificationacademy.com/forums/t/put-a-transaction-into-analysis-fifo/42786/4 "2023-12-06T14:02:42Z")

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_In reply to [m\_v](https://verificationacademy.com/forums/t/put-a-transaction-into-analysis-fifo/42786/3):_

You should never extend the uvm\_sequencer class. The reason for this is that the run\_phase() in the base uvm\_sequencer is required to execute for proper functionality.

You should use a typedef:

```verilog

typedef uvm_sequencer#(spi_transaction) spi_slave_sequencer;

```

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