# NO HANDLE OF VIRTUAL INTERFACE IS RECEIVED

**URL:** <https://verificationacademy.com/forums/t/no-handle-of-virtual-interface-is-received/41692>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, virtual-interface-scoreboard-uvm\
**Created:** [May 23, 2023, 11:21am UTC](https://verificationacademy.com/forums/t/no-handle-of-virtual-interface-is-received/41692 "2023-05-23T11:21:15Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![HoussamSABOUR](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/h/d6d6ee/32.png) [@HoussamSABOUR](https://verificationacademy.com/forums/u/HoussamSABOUR)\
**Post date:** [May 24, 2023, 1:05pm UTC](https://verificationacademy.com/forums/t/no-handle-of-virtual-interface-is-received/41692/3 "2023-05-24T13:05:23Z")

</div>

Thank you Sir,

I try to make it but i have always the same problem, so this is my last code :

```verilog
 $timeformat ( -6, 3, " us", 10);
              uvm_config_db#(virtual ahb_interface)::set(null, "*", "ahb_s0", ahb_s0);
              uvm_config_db#(virtual spi_interface)::set(null, "*", "spi_m0", spi_m0);
  run_test(); 

```

H

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