# Next Cycle Implication operator does not work

**URL:** <https://verificationacademy.com/forums/t/next-cycle-implication-operator-does-not-work/41787>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, assertion, next\_cycle\_implication\_operator\
**Created:** [June 9, 2023, 8:45am UTC](https://verificationacademy.com/forums/t/next-cycle-implication-operator-does-not-work/41787 "2023-06-09T08:45:20Z")\
**Posts on this page:** 1\
**Showing post:** 5

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**Author:** ![UVM\_LOVE](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/uvm_love/32/1684_2.png) [@UVM\_LOVE](https://verificationacademy.com/forums/u/UVM_LOVE)\
**Post date:** [June 10, 2023, 1:17am UTC](https://verificationacademy.com/forums/t/next-cycle-implication-operator-does-not-work/41787/5 "2023-06-10T01:17:56Z")

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_In reply to [ben@SystemVerilog.us](https://verificationacademy.com/forums/t/next-cycle-implication-operator-does-not-work/41787/4):_

Hi Ben,  
Now I’m reading your attached documents, So I think your are trying to tell me about SVA testbench must be conducted on non-blocking domain. so my blocking test sequence in initial statement is wrong.

Please correct me if I wrong.

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