# Multiple clocking block event question

**URL:** <https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [February 19, 2020, 11:41pm UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211 "2020-02-19T23:41:01Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![robert.liu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/bcef8e/32.png) [@robert.liu](https://verificationacademy.com/forums/u/robert.liu)\
**Post date:** [February 24, 2020, 12:24am UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/4 "2020-02-24T00:24:29Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/3):_

Hi Dave, since posedge clk is clocking event for both cb0 and cb1, triggering cb0 and cb1 in observed region as ONE update event or separately? The LRM doesn’t define this at all.

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