# Multiple clocking block event question

**URL:** <https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [February 19, 2020, 11:41pm UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211 "2020-02-19T23:41:01Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [February 20, 2020, 12:33am UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/2 "2020-02-20T00:33:47Z")

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_In reply to [robert.liu](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211):_

The LRM section 14.10 says that your code is equivalent to writing

```verilog
begin: process_x
  @(posedge clk);
  @(posedge clk);
end

```

So it should not be possible to execute in one clock cycle.

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