# Multiple clocking block event question **URL:** \ **Category:** SystemVerilog\ **Tags:** SystemVerilog\ **Created:** [February 19, 2020, 11:41pm UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211 "2020-02-19T23:41:01Z")\ **Posts on this page:** 5\ **Page:** 1
**Author:** ![robert.liu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/bcef8e/32.png) [@robert.liu](https://verificationacademy.com/forums/u/robert.liu)\ **Post date:** [February 19, 2020, 11:41pm UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/1 "2020-02-19T23:41:01Z")
In the design with single clock domain, all the sequential logic is sensitive to one event @(posedge clk). In a testbench for that design, we can have **multiple** clocking blocks defined associated with that DUT clock. Say, clocking cb0 @(posedge clk); clocking cb1 @(posedge clk); If there is some code in a process: begin: process\_x @cb0; @cb1; end Is it possible that simulator triggers cb0 event first, then **immediately** resume the process\_x which would suspend on cb1. Then simulator triggers cb1 at the same clock edge, making the whole process cost only one simulation cycle. ---
**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\ **Post date:** [February 20, 2020, 12:33am UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/2 "2020-02-20T00:33:47Z")
_In reply to [robert.liu](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211):_ The LRM section 14.10 says that your code is equivalent to writing ```verilog begin: process_x @(posedge clk); @(posedge clk); end ``` So it should not be possible to execute in one clock cycle. ---
**Author:** ![robert.liu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/bcef8e/32.png) [@robert.liu](https://verificationacademy.com/forums/u/robert.liu)\ **Post date:** [February 20, 2020, 1:51pm UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/3 "2020-02-20T13:51:45Z")
_In reply to [dave\_59](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/2):_ The LRM section 14.13 says > Upon processing its specified clocking event, a clocking block shall update its sampled values before triggering **the event associated with the clocking block name. This event shall be triggered in the _Observed region_**. Seems this is small but important difference between @cb and its associated @(posedge clk). when simulator sees posedge clk event in the active region, it schedule trigger of clocking block events into the observed event queue. And when simulator executes events from the observed event queue, it copy the events into the active region and execute them from there. > while (any region in [Active … Post-Observed] is nonempty) { > execute\_region (Active); > R = first nonempty region in [Active … Post-Observed]; > if (R is nonempty) > move events in R to the Active region; > } I have a fundamental question about this reference algorithm. Is event from the active region executed **in place** in the active event region OR the events get copied out of the active region to a temporary buffer essentially making the active region empty before the event execution? Because event triggering might resume more suspended processes which would be put into active region. I wonder evaluation(execution) of these processes are in the next round of active region scheduling or right in the same round of event triggering. ---
**Author:** ![robert.liu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/bcef8e/32.png) [@robert.liu](https://verificationacademy.com/forums/u/robert.liu)\ **Post date:** [February 24, 2020, 12:24am UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/4 "2020-02-24T00:24:29Z")
_In reply to [dave\_59](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/3):_ Hi Dave, since posedge clk is clocking event for both cb0 and cb1, triggering cb0 and cb1 in observed region as ONE update event or separately? The LRM doesn’t define this at all. ---
**Author:** ![robert.liu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/bcef8e/32.png) [@robert.liu](https://verificationacademy.com/forums/u/robert.liu)\ **Post date:** [February 24, 2020, 12:38am UTC](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/5 "2020-02-24T00:38:00Z")
_In reply to [dave\_59](https://verificationacademy.com/forums/t/multiple-clocking-block-event-question/37211/4):_ If cb0 and cb1 are triggered from separate event from Observed region, then according to the reference simulation algorithm, ```verilog execute_region { while (region is nonempty) { E = any event from region; remove E from the region; if (E is an update event) { update the modified object; schedule evaluation event for any process sensitive to the object; } else { /* E is an evaluation event */ evaluate the process associated with the event and possibly schedule further events for execution; } } } ``` The following steps are possible: 0. move all events from observed region to active region 1. cb0 update event is removed from active region and executed. The cb0 gets triggered; evaluation event for process\_x execution is scheduled into active region 2. process\_x move forward and wait for @cb1. process\_x get suspended 3. cb1 update event is removed from active region and executed. The cb1 gets triggered; evaluation event for process\_x execution is scheduled into active region 4. process\_x move forward and finish. This way the whole process\_x only consumes one cycle.