# Loops inside Function new in OVM

**URL:** <https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363>\
**Category:** OVM\
**Tags:** OVM, function-new, Cookbook-OVMPhasing\
**Created:** [April 19, 2018, 10:42am UTC](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363 "2018-04-19T10:42:55Z")\
**Posts on this page:** 6\
**Page:** 1

<div class="post-metadata">

**Author:** ![SivaNamathoti](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/c2a13f/32.png) [@SivaNamathoti](https://verificationacademy.com/forums/u/SivaNamathoti)\
**Post date:** [April 19, 2018, 10:42am UTC](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/1 "2018-04-19T10:42:55Z")

</div>

function new (string str=“pmc\_svt\_i2c\_system\_configuration”);  
super.new(str);

```
num_slaves = 128; // 128 new slaves
int i;
/** Create port configurations */
create_sub_cfgs(num_masters, num_slaves);

  for(i=32'h20 ; i < 32'h60 ; i ++) begin
     slave_cfg[i].is_active = 0;
     slave_cfg[i].slave_address = i[9:0]; // `SVT_I2C_SLAVE0_ADDRESS; 
     slave_cfg[i].bus_speed = HIGHSPEED_MODE;
     slave_cfg[i].enable_10bit_addr = 0;
  end

```

endfunction

On compiling the above code, the following error is thrown.

Error-[SE] Syntax error  
Following verilog source has syntax error :  
“/nfs/fm/disks/001/config.sv”,  
22: token is ‘int’  
int i;  
^  
System verilog keyword ‘int’ is not expected to be used in this context.

Why can’t we use the variable int or bit in the function new?

---

<div class="post-metadata">

**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [April 19, 2018, 11:33am UTC](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/2 "2018-04-19T11:33:52Z")

</div>

_In reply to [Siva Namathoti](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363):_

You can, but SystemVerilog requires all variable declarations precede all procedural code. The statement ‘num\_slaves = 128;’ is procedural, so declaring ‘int i’ can not come after it. Move the declaration of ‘i’ to the top of the function.

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<div class="post-metadata">

**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [April 19, 2018, 1:50pm UTC](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/3 "2018-04-19T13:50:57Z")

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_In reply to [cgales](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/2):_  
You also move the declaration of ‘I’ as part of the for loop statement. Then it becomes a local variable to the **for** loop block.

```verilog
for(int i=32'h20 ; i < 32'h60 ; i ++) begin

```

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<div class="post-metadata">

**Author:** ![ShaikhAbuzar](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/f17d59/32.png) [@ShaikhAbuzar](https://verificationacademy.com/forums/u/ShaikhAbuzar)\
**Post date:** [November 25, 2022, 1:07pm UTC](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/4 "2022-11-25T13:07:40Z")

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_In reply to [cgales](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/3):_  
This might sound very silly question but anyway…  
How num\_slaves =128 is procedural code?

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<div class="post-metadata">

**Author:** ![ABD\_91](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/c77e96/32.png) [@ABD\_91](https://verificationacademy.com/forums/u/ABD_91)\
**Post date:** [November 25, 2022, 1:15pm UTC](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/5 "2022-11-25T13:15:58Z")

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_In reply to [Abuzar Gaffari](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/4):_

Function , task , initial are procedural blocks .

Constructor ( new ) is a function so statements written within them are procedural .

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<div class="post-metadata">

**Author:** ![ABD\_91](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/c77e96/32.png) [@ABD\_91](https://verificationacademy.com/forums/u/ABD_91)\
**Post date:** [November 25, 2022, 1:31pm UTC](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/6 "2022-11-25T13:31:24Z")

</div>

_In reply to [cgales](https://verificationacademy.com/forums/t/loops-inside-function-new-in-ovm/34363/5):_

Since SystemVerilog allows user to declare variables **within begin … end block**  
the variable **i could be also defined as following right ?** ::

```verilog

function new (string str="pmc_svt_i2c_system_configuration");
  super.new(str);

  num_slaves = 128; // 128 new slaves
 
 begin // Added to declare variable(s)  
   int i;
   // Remaining code here
 end

endfunction

```