# Logic keyword

**URL:** <https://verificationacademy.com/forums/t/logic-keyword/39041>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, logic\
**Created:** [May 3, 2021, 2:42pm UTC](https://verificationacademy.com/forums/t/logic-keyword/39041 "2021-05-03T14:42:31Z")\
**Posts on this page:** 1\
**Showing post:** 3

<div class="post-metadata">

**Author:** ![damera](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/d/e274bd/32.png) [@damera](https://verificationacademy.com/forums/u/damera)\
**Post date:** [May 4, 2021, 7:30am UTC](https://verificationacademy.com/forums/t/logic-keyword/39041/3 "2021-05-04T07:30:59Z")

</div>

_In reply to [dave\_59](https://verificationacademy.com/forums/t/logic-keyword/39041/2):_  
Hi Dave ,  
Thank you so much for the reply.  
After reading the blog, I understood that a logic varibale can’t be driven with a continous and procedural statement at a time which is Ex3. (Please correct me if I am wrong)  
Below are the few examples I tried. Please explain me why the display is 10 in Ex2 and error in Ex1  
Replacing logic with wire in Ex1 is also giving me the same error. Please explain me why.  
Ex1:

```verilog
module dut;  
   logic [7:0] x;  
   assign x = 5;  
   assign x = 10;  
   initial $display("%0d",x);  
endmodule

```

Output: complie time error  
(vlog-7045) ‘x’ is driven by more than one continuous assignment.  
Ex2:

```verilog
module dut;  
   logic [7:0] x;  
   initial x = 5;  
   initial x = 10;  
   initial $display("%0d",x);  
endmodule

```

Output: 10  
Ex3:

```verilog
module dut;  
   logic [7:0] x;  
   initial x = 5;  
   assign x = 10;  
   initial $display("%0d",x);  
endmodule

```

Output: complilation error  
(vlog-12003) Variable ‘x’ written by continuous and procedural assignments.

---

_[View the full topic](https://verificationacademy.com/forums/t/logic-keyword/39041)._