# I am new to UVM.How can collect packet stored in a queue as a sequence in one by one manner and run over a sequencer in uvm? Sequence body is given,build phase of the sequencer is given with getting handle of component with queue.help to solve this

**URL:** <https://verificationacademy.com/forums/t/i-am-new-to-uvm-how-can-collect-packet-stored-in-a-queue-as-a-sequence-in-one-by-one-manner-and-run-over-a-sequencer-in-uvm-sequence-body-is-given-build-phase-of-the-sequencer-is-given-with-getting-handle-of-component-with-queue-help-to-solve-this/39028>\
**Category:** UVM\
**Tags:** UVM, getting-a-fixed-sequence-from-a-queue-to-a-sequencer\
**Created:** [April 28, 2021, 3:43pm UTC](https://verificationacademy.com/forums/t/i-am-new-to-uvm-how-can-collect-packet-stored-in-a-queue-as-a-sequence-in-one-by-one-manner-and-run-over-a-sequencer-in-uvm-sequence-body-is-given-build-phase-of-the-sequencer-is-given-with-getting-handle-of-component-with-queue-help-to-solve-this/39028 "2021-04-28T15:43:57Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![nithya\_jinu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/n/a3d4f5/32.png) [@nithya\_jinu](https://verificationacademy.com/forums/u/nithya_jinu)\
**Post date:** [April 28, 2021, 3:43pm UTC](https://verificationacademy.com/forums/t/i-am-new-to-uvm-how-can-collect-packet-stored-in-a-queue-as-a-sequence-in-one-by-one-manner-and-run-over-a-sequencer-in-uvm-sequence-body-is-given-build-phase-of-the-sequencer-is-given-with-getting-handle-of-component-with-queue-help-to-solve-this/39028/1 "2021-04-28T15:43:57Z")

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task body();

my\_sequencer = get\_sequencer();

ERROR\_bad\_ace\_axi\_pkt: assert (!($cast(axi3\_pkt, ace\_axi\_pkt)));

`uvm\_sent(ace\_axi\_pkt)

endtask

function void build\_phase(uvm\_phase phase);  
super.build\_phase(phase);

//Getting the ace\_snoop\_agent configuration object from environment inside axi3sequencer  
//------------------------------------------------------------------------  
if(!uvm\_config\_db #(ace\_snoop\_agent\_cfg) ::get(this,“”,“ace\_snoop\_agent\_cfg”,ace\_snoop\_agent\_cfg\_h))  
`uvm\_fatal(get\_full\_name(),“The sequencer didn’t get the ace snoop agent config object handle”)

endfunction

---

<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [April 29, 2021, 3:27pm UTC](https://verificationacademy.com/forums/t/i-am-new-to-uvm-how-can-collect-packet-stored-in-a-queue-as-a-sequence-in-one-by-one-manner-and-run-over-a-sequencer-in-uvm-sequence-body-is-given-build-phase-of-the-sequencer-is-given-with-getting-handle-of-component-with-queue-help-to-solve-this/39028/2 "2021-04-29T15:27:22Z")

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_In reply to [nithya jinu](https://verificationacademy.com/forums/t/i-am-new-to-uvm-how-can-collect-packet-stored-in-a-queue-as-a-sequence-in-one-by-one-manner-and-run-over-a-sequencer-in-uvm-sequence-body-is-given-build-phase-of-the-sequencer-is-given-with-getting-handle-of-component-with-queue-help-to-solve-this/39028):_

Could you please show some more code to clarify your problem?  
You do not store data packets(seq\_items) on the generation side in a queue.  
You are instructing your sequence to do this in a one-by-one manner when the processing of the actual packet has been completed.

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**Author:** ![sa5691](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/7feea3/32.png) [@sa5691](https://verificationacademy.com/forums/u/sa5691)\
**Post date:** [April 30, 2021, 6:42am UTC](https://verificationacademy.com/forums/t/i-am-new-to-uvm-how-can-collect-packet-stored-in-a-queue-as-a-sequence-in-one-by-one-manner-and-run-over-a-sequencer-in-uvm-sequence-body-is-given-build-phase-of-the-sequencer-is-given-with-getting-handle-of-component-with-queue-help-to-solve-this/39028/3 "2021-04-30T06:42:32Z")

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You should do this in driver.

```verilog

```

```verilog
class t_driver extends uvm_driver #(packet);
  virtual intf vif_tb;

  static int txn_cnt;
  
  packet txn[$];
virtual task run_phase(uvm_phase phase);
    
    @(vif_tb.cb); // Give one clock to allow propagation of clocking block
    
      drive_address(txn);
     
   
    forever begin
      seq_item_port.get_next_item(req);
      `uvm_info(get_full_name(), "Driver got a sequence item", UVM_MEDIUM);

      txn.push_back(req);
    

      seq_item_port.item_done();
    end
 

  task automatic drive_address(packet txn[$]);

  endtask

```

```verilog

```