# How to use assign inside $test$plusargs in systemverilog?

**URL:** <https://verificationacademy.com/forums/t/how-to-use-assign-inside-test-plusargs-in-systemverilog/37829>\
**Category:** SystemVerilog\
**Tags:** UVM, SystemVerilog, Verilog\
**Created:** [July 11, 2020, 8:41am UTC](https://verificationacademy.com/forums/t/how-to-use-assign-inside-test-plusargs-in-systemverilog/37829 "2020-07-11T08:41:15Z")\
**Posts on this page:** 1\
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**Author:** ![GC](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/g/e95f7d/32.png) [@GC](https://verificationacademy.com/forums/u/GC)\
**Post date:** [July 11, 2020, 8:55pm UTC](https://verificationacademy.com/forums/t/how-to-use-assign-inside-test-plusargs-in-systemverilog/37829/3 "2020-07-11T20:55:26Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/how-to-use-assign-inside-test-plusargs-in-systemverilog/37829/2):_

I tried using “z” since its a wire but in that case i see it stays z, the value to this wire “hb\_valid\_in” is being provided from the sequence in this particular testcase and I don’t want it to be overriden by this assign. In this case its not taking the value from sequence but it stays z but if I don’t do assign at all for this particular case, it works so I was looking for a way to not do these assigns for a particular test, not sure if this is doable.

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