How to config the variable in uvm_component (e.g. uvm_monitor) by the sequence?

UVM
1

Hi,

Is there a good way to config the variable of the monitor while in the task body() of the sequence?

class my_monitor extends uvm_monitor; 

    bit check_enable = 1;

    virtual task run_phase(uvm_phase phase);
        if (check_enable) begin
            // checking
        end
    endtask

endclass


class my_seq extends uvm_sequence;

    virtual task body();
        ...
        // Set my_monitor.check_enable = 0
        ...
        // Set my_monitor.check_enable = 1
    endtask

endclass
2

You need the following
(1) Within a forever loop use uvm_config_db#(bit)::wait_modified( this ,“” , “enable_bit” ) followed by uvm_config_db#(bit)::get( this ,“” , “enable_bit” , check_enable ) as a separate thread in my_monitor to fetch

(2) Within body() task ::

check_enable = 0;
uvm_config_db#(bit)::set(null,"uvm_test_top.env_h.agent_h.monitor_h","enable_bit",check_enable);
.......
check_enable = 1;
uvm_config_db#(bit)::set(null,"uvm_test_top.env_h.agent_h.monitor_h","enable_bit",check_enable);
1 Like
3

Using the config_db() in this manner is not recommended. The config_db() is designed to pass configuration data down the testbench hierarchy at time 0, not to pass data between components while the testbench is running.

I would argue that there should be no need to enable/disable your monitor functionality at any time. The monitor should be aware when the data it is monitoring is valid (reset signal/data valid signal, etc.).

If you really feel the need to alter the behavior of your monitor, add an element to your agent’s configuration object. You can then also pass the configuration object to your sequence and modify as required.

4

Hi @cgales ,

Actually, it’s that I would like to disable some of the checking in the monitor for the error injection cases. So, what is a better approach instead?

Thanks

5

If you are running a test which generates error scenarios, then you should configure the agent’s configuration object to disable the desired checks as part of the test.

1 Like