# How is it possible to do a write as well as read using a apb slave?

**URL:** <https://verificationacademy.com/forums/t/how-is-it-possible-to-do-a-write-as-well-as-read-using-a-apb-slave/37006>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [January 10, 2020, 7:03pm UTC](https://verificationacademy.com/forums/t/how-is-it-possible-to-do-a-write-as-well-as-read-using-a-apb-slave/37006 "2020-01-10T19:03:27Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Arun\_Rajha](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/35a633/32.png) [@Arun\_Rajha](https://verificationacademy.com/forums/u/Arun_Rajha)\
**Post date:** [January 10, 2020, 7:03pm UTC](https://verificationacademy.com/forums/t/how-is-it-possible-to-do-a-write-as-well-as-read-using-a-apb-slave/37006/1 "2020-01-10T19:03:27Z")

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I have tried a apb slave, can there be a apb master or a apb slave right? is it possible for a same bus to act as master and slave at different instance, so should i need to write a apb\_master dut separately and apb\_slave dut separately? . please clarify me as i am new to building interfaces. can anyone give me a perfect example to connect how transfers happen between a apb master and slave?

module apb\_slave  
#(  
addrWidth = 8,  
dataWidth = 32  
)  
(  
input clk,  
input rst\_n,  
input [addrWidth-1:0] paddr,  
input pwrite,  
input psel,  
input penable,  
input [dataWidth-1:0] pwdata,  
output logic [dataWidth-1:0] prdata  
);

logic [dataWidth-1:0] mem [256];

logic [1:0] apb\_st;  
const logic [1:0] SETUP = 0;  
const logic [1:0] W\_ENABLE = 1;  
const logic [1:0] R\_ENABLE = 2;

// SETUP → ENABLE  
always @(negedge rst\_n or posedge clk) begin  
if (rst\_n == 0) begin  
apb\_st \<= 0;  
prdata \<= 0;  
end

else begin  
case (apb\_st)  
SETUP : begin  
// clear the prdata  
prdata \<= 0;

```
    // Move to ENABLE when the psel is asserted
    if (psel && !penable) begin
      if (pwrite) begin
        apb_st <= W_ENABLE;
      end

      else begin
        apb_st <= R_ENABLE;
      end
    end
  end

  W_ENABLE : begin
    // write pwdata to memory
    if (psel && penable && pwrite) begin
      mem[paddr] <= pwdata;
    end

    // return to SETUP
    apb_st <= SETUP;
  end

  R_ENABLE : begin
    // read prdata from memory
    if (psel && penable && !pwrite) begin
      prdata <= mem[paddr];
    end

    // return to SETUP
    apb_st <= SETUP;
  end
endcase

```

end  
end  
initial  
begin  
$dumpfile(“test.vcd”);  
$dumpvars;  
end

endmodule

---

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**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [January 10, 2020, 9:40pm UTC](https://verificationacademy.com/forums/t/how-is-it-possible-to-do-a-write-as-well-as-read-using-a-apb-slave/37006/2 "2020-01-10T21:40:14Z")

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_In reply to [Arun\_Rajha](https://verificationacademy.com/forums/t/how-is-it-possible-to-do-a-write-as-well-as-read-using-a-apb-slave/37006):_

It has been since 2004 that I last looked at that interface, thus I hardly remember anything about it. However, at that time I published the book _Using PSL/Sugar for Formal and Dynamic Verification 2nd Edition_ where in Chapter 8 I addressed the design and verification of the AHB. Specifically, the chapter demonstrates how an AMBA™ AHB bus specification1 and an IDT 71V433 Synchronous pipelined SRAM2 are used to design and verify a memory slave controller in Verilog and PSL. Simulation with a PSL aware simulator was used for verification. The testbench does not have an automatic verifier, which is included in a traditional self-checking methodology. Instead, verification relies on ABV methodology.

[http://systemverilog.us/vf/PSL\_AHB\_Ch8.zip](http://systemverilog.us/vf/PSL_AHB_Ch8.zip)  
This link provides the PDF for that chapter and all the Verilog code used in the process.  
Reading the PDF and the code may help you better understand the interface and the requirements.

BTW, I DO NOT recommend the use of PSL; use SystemVerilog instead.

Ben Cohen  
[http://www.systemverilog.us/](http://www.systemverilog.us/) [ben@systemverilog.us](mailto:ben@systemverilog.us)  
For training, consulting, services: contact [Home - My cvcblr](http://cvcblr.com/home)

- [SVA Handbook 4th Edition, 2016 ISBN 978-1518681448](http://goo.gl/JOfuEB)
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- [Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712](https://goo.gl/d10QHh)
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

* * *

1. SVA Alternative for Complex Assertions  
[Verification Horizons - March 2018 Issue | Verification Academy](https://verificationacademy.com/news/verification-horizons-march-2018-issue)
2. [SVA: Package for dynamic and range delays and repeats | Verification Academy](https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats)
3. SVA in a UVM Class-based Environment  
[SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy](https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment)