# How do you ensure no race condition occurs?

**URL:** <https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, Race-condition\
**Created:** [June 11, 2014, 5:46am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575 "2014-06-11T05:46:16Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [June 11, 2014, 6:17am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/2 "2014-06-11T06:17:53Z")

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_In reply to [Reuben](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575):_

It would help if you could explain how sigs.sentMon.sent\_sdin is defined and how it changes value.

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