# How do you ensure no race condition occurs?

**URL:** <https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, Race-condition\
**Created:** [June 11, 2014, 5:46am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575 "2014-06-11T05:46:16Z")\
**Posts on this page:** 7\
**Page:** 1

<div class="post-metadata">

**Author:** ![Reuben](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/reuben/32/1409_2.png) [@Reuben](https://verificationacademy.com/forums/u/Reuben)\
**Post date:** [June 11, 2014, 5:46am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/1 "2014-06-11T05:46:16Z")

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How do you ensure no race condition occurs?

Let’s take the example below. In that example, I’m trying to count the number of clock cycles between the negedge of sent\_sdin.  
So the possible problem here is to have a race condition of the assignment of variable in\_between\_negedge.

```verilog

fork
// Detect send_sdin negedge
forever begin
  @(negedge sigs.sentMon.sent_sdin);
  `uvm_info("sent_monitor", $sformatf("sent_sdin first negedge!"), UVM_MEDIUM);
  in_between_negedge = 1;
        
  @(negedge sigs.sentMon.sent_sdin);
  `uvm_info("sent_monitor", $sformatf("sent_sdin second negedge!"),UVM_MEDIUM);

  in_between_negedge = 0;
end

forever begin
  wait(in_between_negedge);

  // Race condition may happen here. When negedge of sent_sdin comes, the while-loop may
  // not be able to get a 0 value for in_between_negedge. So cnt_pulse will become 1 greater
  // than the correct value.
  while(in_between_negedge) begin
    @(posedge sigs.ecu_clk);
    ++cnt_pulse;
  end
end
join_any

```

Here’s the interface where sent\_sdin is located. I don’t clocking block.

```verilog

interface sent_if (input ecu_clk);
  logic rstb;
  logic sent_en;
  logic sent_sdin;
  logic sent_sdout_hi;
  logic sent_sdout_lo;
  logic sent_rx_enb;
  logic sent_tx_enb; 
endinterface

```

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<div class="post-metadata">

**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [June 11, 2014, 6:17am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/2 "2014-06-11T06:17:53Z")

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_In reply to [Reuben](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575):_

It would help if you could explain how sigs.sentMon.sent\_sdin is defined and how it changes value.

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<div class="post-metadata">

**Author:** ![Reuben](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/reuben/32/1409_2.png) [@Reuben](https://verificationacademy.com/forums/u/Reuben)\
**Post date:** [June 11, 2014, 6:28am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/3 "2014-06-11T06:28:48Z")

</div>

_In reply to [dave\_59](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/2):_

Oh ok. I think I’ll just edit it. Actually those signals are form the monitor.

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<div class="post-metadata">

**Author:** ![Reuben](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/reuben/32/1409_2.png) [@Reuben](https://verificationacademy.com/forums/u/Reuben)\
**Post date:** [June 11, 2014, 6:34am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/4 "2014-06-11T06:34:52Z")

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_In reply to [Reuben](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/3):_

The driver drives sent\_sdin after seeing the posedge of clk.

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<div class="post-metadata">

**Author:** ![Reuben](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/reuben/32/1409_2.png) [@Reuben](https://verificationacademy.com/forums/u/Reuben)\
**Post date:** [June 11, 2014, 6:38am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/5 "2014-06-11T06:38:06Z")

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_In reply to [Reuben](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/4):_

Actually this is just a theoretical situation. I don’t really have that code. I’m just worrying that if I implement it then it might have race condition so I’m looking for a way to avoid it.

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<div class="post-metadata">

**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [June 11, 2014, 3:56pm UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/6 "2014-06-11T15:56:37Z")

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The recommendation here is to write code that is synchronous to only one clock edge, do not use mixtures of different signal edges and wait statements. Only use

@(posedge sigs.ecu\_clk); or @(posedge sigs.ecu\_clk iff (signal == value));

The signals that you sample must be written with non-blocking assignments, just like RTL designers would do to avoid race conditions, or you can use clocking blocks to sample the signals. Once you start using clocking blocks, you should only use the clocking block event to synchronize your code.

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<div class="post-metadata">

**Author:** ![Reuben](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/reuben/32/1409_2.png) [@Reuben](https://verificationacademy.com/forums/u/Reuben)\
**Post date:** [June 12, 2014, 5:18am UTC](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/7 "2014-06-12T05:18:04Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/how-do-you-ensure-no-race-condition-occurs/29575/6):_

Okay. Thanks. I think that’s a better way of coding.  
I’m not using clocking blocks that’s why race conditions are so frequent.  
Hmm… Seems I need to do a lot of changes in my testbench. =)