# How can i increase the simulation time in UVM

**URL:** <https://verificationacademy.com/forums/t/how-can-i-increase-the-simulation-time-in-uvm/32832>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [February 9, 2017, 4:48pm UTC](https://verificationacademy.com/forums/t/how-can-i-increase-the-simulation-time-in-uvm/32832 "2017-02-09T16:48:52Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![shankar\_logic](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/edb3f5/32.png) [@shankar\_logic](https://verificationacademy.com/forums/u/shankar_logic)\
**Post date:** [February 9, 2017, 4:48pm UTC](https://verificationacademy.com/forums/t/how-can-i-increase-the-simulation-time-in-uvm/32832/1 "2017-02-09T16:48:52Z")

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Hi,

I have integrated a UVM testbench with the VHDL design. But the issue occurs due to the end of the simulation at 150 ps whereas i have given in the top file.

module tb\_top

initial  
begin  
#10000 $finish;  
end  
endmodule

So, the simulation should end at 10000ps.

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**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [February 9, 2017, 5:40pm UTC](https://verificationacademy.com/forums/t/how-can-i-increase-the-simulation-time-in-uvm/32832/2 "2017-02-09T17:40:07Z")

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_In reply to [shankar\_logic](https://verificationacademy.com/forums/t/how-can-i-increase-the-simulation-time-in-uvm/32832):_

You should read the section on the Verification Academy on how [UVM determines the end of a test](https://verificationacademy.com/cookbook/endoftest).

If your UVM test ends, your simulation will also end.

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**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [February 9, 2017, 6:31pm UTC](https://verificationacademy.com/forums/t/how-can-i-increase-the-simulation-time-in-uvm/32832/3 "2017-02-09T18:31:32Z")

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_In reply to [shankar\_logic](https://verificationacademy.com/forums/t/how-can-i-increase-the-simulation-time-in-uvm/32832/2):_

What #10000 means depends on the time resolution, i.e. it does not mean 150 ps in any case.  
But UVM provides you with the objection mechanism which stops the simulation after finishing the corresponding test. If you do not implement the objections your simulation comes at time 0 to the end.  
Never use an absolut time with $finish/$stop to finish the simulation.

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**Author:** ![shankar\_logic](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/edb3f5/32.png) [@shankar\_logic](https://verificationacademy.com/forums/u/shankar_logic)\
**Post date:** [February 9, 2017, 7:09pm UTC](https://verificationacademy.com/forums/t/how-can-i-increase-the-simulation-time-in-uvm/32832/4 "2017-02-09T19:09:12Z")

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Thanks it worked for my testbench