Global assignment in interface function statement

Hi there!

I create cnt_if below and I want to use the connect functoin in fpga_top module.
It’s work on simulation but I get Mandatory on spyglass lint check.
The error is No: STARC05-2.1.3.5, “Global variable “load” is assigned in a funcion description.”
I think there is no problem this usecase if the “global” scope is within cnt_if.
Is there any other problem in the code?

!!! I modified below at 24/7/11 !!!

interface cnt_if #(parameter int BW = 14)();
  logic load, enable, reset;
  logic [BW-1:0] cnt;

  function automatic void connect(ld, en = 1'b1, rst = 1'b0);
    load = ld;
    enable = en;
    reset = rst;
  endfunction
endinterface

module counter (input wire clk, cnt_if pt);
  always_ff @ (posedge clk)
    if(pt.load) pt.cnt <= '0;
    else        pt.cnt <= pt.cnt + 'b1;
endmodule

module fpga_top (
  input wire clk,
  input wire id,
  output wire [9:0] od
);

cnt_if #(.BW(10)) cnt_if();
counter counter(.clk, .pt(cnt_if));

always_comb begin
  cnt_if.connect(.ld(id));
end
assign od = cnt_if.cnt;
endmodule

module top;

bit clk;
initial forever #10 clk = ~clk;

logic data;
cnt_if cnt_if();
counter counter(.clk, .pt(cnt_if));

always_comb begin
  cnt_if.connect(.ld(data));
end

  initial begin
    data = 1'b0;
    #(100);
    data = 1'b1;
    #(100);
    data = 1'b0;
    #(1000);
    $strobe("finish!");
    $finish;
  end
endmodule

I use “top” module for simulation, and “fpga_top” module for lint check.
simulator: questasim2024.1

Could that be because the function is defined as automatic, hence, load variable might have multiple values at the same time, which means, it can’t be assigned inside an automatic function?

If that is the case, then maybe defining an output parameter at the function definition, then assign that output parameter upon calling the function, might be a workaround?

The code you posted does not compile in any simulation tool. You have only defined load inside the interface cnt_if. It is not a global signal.

Thanks for replying, and I’m sorry for the code I posted on the topic is not work.
I modified the topic’s code.

As you said, I modified the code below.
The global signal error on lint check is cleared but the code is wasteful I think.
I want to set load,enable,reset value directly but does it not recommend?


interface cnt_if #(parameter int BW = 14)();
  typedef struct packed {
    logic load, enable, reset;
  } stim_t;
  stim_t stim;
  logic [BW-1:0] cnt;

  function automatic void connect(output stim_t od, input logic ld, en = 1'b1, rst = 1'b0);
    od.load = ld;
    od.enable = en;
    od.reset = rst;
  endfunction
endinterface

module counter (input wire clk, cnt_if pt);
  always_ff @ (posedge clk)
    if(pt.stim.load)  pt.cnt <= '0;
    else              pt.cnt <= pt.cnt + 'b1;
endmodule

module fpga_top (
  input wire clk,
  input wire id,
  output wire [9:0] od
);

cnt_if #(.BW(10)) cnt_if();
counter counter(.clk, .pt(cnt_if));

always_comb begin
  cnt_if.connect(.od(cnt_if.stim), .ld(id));
end
assign od = cnt_if.cnt;
endmodule

Thanks for replying, and I’m sorry for the code I posted on the topic is not work.
I modified the topic’s code.
The “global” maybe means “Referencing an external variable from within a function” but dose it have any problem?

You have a tool related issue. The code you show looks fine.

This Siemens sponsored public forum is not for discussing tool specific issues. Please read your tool’s User Manual or contact your tool vendor for support.

Ok, thanks for your replying!