# Getting an compilation error on concurrent assertion

**URL:** <https://verificationacademy.com/forums/t/getting-an-compilation-error-on-concurrent-assertion/30174>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [November 27, 2014, 4:08am UTC](https://verificationacademy.com/forums/t/getting-an-compilation-error-on-concurrent-assertion/30174 "2014-11-27T04:08:12Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![rajput7767](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/5fc32e/32.png) [@rajput7767](https://verificationacademy.com/forums/u/rajput7767)\
**Post date:** [November 27, 2014, 4:08am UTC](https://verificationacademy.com/forums/t/getting-an-compilation-error-on-concurrent-assertion/30174/1 "2014-11-27T04:08:12Z")

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Hi,

I have written an assertion mentioned below:

1. property clk\_stop;
2. @ (negedge `CLK_STP_CLK_PATH.clkext2f) disable iff (!tb_A9Platform.assertions_on) !`CLK\_STP\_PATH.nCPURESET ##1 `CLK_STP_PATH.nCPURESET |-> (`CLK\_STP\_PATH.CLK == 1’b0)[\*3] ##1 (`CLK\_STP\_PATH.CLK == 1’b1);
3. endproperty

clk\_stop\_assertion : assert property (clk\_stop)  
else $display(“clk\_stop\_assertion failed for hold the clk zero for total of three cycles”);

I am getting the following compilation error.

Expecting the keyword endmodule at line 2, though i have written endmodule for my module.  
Please help.

Regards,  
Shailendra