# Functional coverage in testbench

**URL:** <https://verificationacademy.com/forums/t/functional-coverage-in-testbench/30192>\
**Category:** Coverage\
**Tags:** Coverage\
**Created:** [December 3, 2014, 9:08am UTC](https://verificationacademy.com/forums/t/functional-coverage-in-testbench/30192 "2014-12-03T09:08:47Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Ashok1](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/f1d935/32.png) [@Ashok1](https://verificationacademy.com/forums/u/Ashok1)\
**Post date:** [December 3, 2014, 9:08am UTC](https://verificationacademy.com/forums/t/functional-coverage-in-testbench/30192/1 "2014-12-03T09:08:47Z")

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Hi,

How can we write functional coverage for verilog testbench.i can write cover-groups inside a module and trigger cover groups,apart from this is there any standard apporach?

Thanks in Advance,  
Nawaz

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [December 3, 2014, 10:04pm UTC](https://verificationacademy.com/forums/t/functional-coverage-in-testbench/30192/2 "2014-12-03T22:04:18Z")

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The standard approach for writing testbenches with functional coverage is to use a monitor that sends transactions to a coverage collector with the UVM. Just because your testbench is Verilog (which is just SystemVerilog without classes) does not prevent you from adding a class based monitor.