# Enumarated data types

**URL:** <https://verificationacademy.com/forums/t/enumarated-data-types/38538>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, enum\
**Created:** [January 5, 2021, 7:44am UTC](https://verificationacademy.com/forums/t/enumarated-data-types/38538 "2021-01-05T07:44:09Z")\
**Posts on this page:** 1\
**Showing post:** 3

<div class="post-metadata">

**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [January 5, 2021, 4:50pm UTC](https://verificationacademy.com/forums/t/enumarated-data-types/38538/3 "2021-01-05T16:50:51Z")

</div>

_In reply to [Shivansh Bhardwaj](https://verificationacademy.com/forums/t/enumarated-data-types/38538/2):_  
See 1800’2017 **6.19 Enumerations**  
The bottom line: It make the code mode readable. For example:

```verilog

typedef enum {NOP, ADD, SUB, MULT, JMP, MOV, READ, WRITE, IDLE} instr_e;
typedef enum {FETCH, DECODE, EXECUTE} mode_e;
typedef enum {PC, IR1, IR2, REGA, REGB, MAR, REG_FILE, STK} resource_e;
instr_e instr; 
if(instr==READ) ...

// You can assign values to these elements 
// The values can be cast to integer types and increment from an initial value of 0. This can be overridden.
enum {bronze=3, silver, gold} medal; // silver=4, gold=5

```

Ben Cohen  
[http://www.systemverilog.us/](http://www.systemverilog.us/) [ben@systemverilog.us](mailto:ben@systemverilog.us)  
For training, consulting, services: contact [http://cvcblr.com/home.html](http://cvcblr.com/home.html)  
\*\* SVA Handbook 4th Edition, 2016 ISBN 978-1518681448  
…

1. SVA Package: Dynamic and range delays and repeats [SVA: Package for dynamic and range delays and repeats | Verification Academy](https://rb.gy/a89jlh)
2. Free books: Component Design by Example [FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy](https://rb.gy/9tcbhl)  
Real Chip Design and Verification Using Verilog and VHDL($3) [Amazon.com](https://rb.gy/cwy7nb)
3. Papers:

- Understanding the SVA Engine,  
[Verification Horizons - July 2020 | Verification Academy](https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2)
- SVA Alternative for Complex Assertions  
[Verification Horizons - March 2018 Issue | Verification Academy](https://verificationacademy.com/news/verification-horizons-march-2018-issue)
- SVA in a UVM Class-based Environment  
[SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy](https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment)

---

_[View the full topic](https://verificationacademy.com/forums/t/enumarated-data-types/38538)._