# Define vs. parameter - difference

**URL:** <https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [May 1, 2020, 5:50pm UTC](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527 "2020-05-01T17:50:38Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![MichaelP](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/m/58f4c7/32.png) [@MichaelP](https://verificationacademy.com/forums/u/MichaelP)\
**Post date:** [May 1, 2020, 5:50pm UTC](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527/1 "2020-05-01T17:50:38Z")

</div>

Hi,

What are the differences between using define and parameter?  
Aside of the fact that the parameter is like a const and `define is compiler directive.  
Is there any difference from runtime point of view?

```verilog

`define NUM_OF_PROFILES 1024
parameter MAX_NUM_OF_PROFILES = 2048;

```

Thanks in advance!

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**Author:** ![rgarcia07](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/a87d85/32.png) [@rgarcia07](https://verificationacademy.com/forums/u/rgarcia07)\
**Post date:** [May 1, 2020, 6:37pm UTC](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527/2 "2020-05-01T18:37:12Z")

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_In reply to [Michael54](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527):_

Macros are basically text substitutions, this will be expanded during compile time, Parameters on the other hand are just constants that are resolved at elaboration time.

With macros you can do things like:

`define MAX(p,q) (p)>(q)?(p):(q) ... #`MAX(delay1, delay2);

HTH,

-R

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [May 1, 2020, 7:42pm UTC](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527/3 "2020-05-01T19:42:26Z")

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_In reply to [rgarcia07](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527/2):_

Macros _ARE_ just text substitutions. They do appear to have overlapping functionality, so in Michael54’s example, there is no difference in runtime execution.

Macros, parameters, and const variables all have features available in some but not others.

const variables get initialized once at the beginning of their lifetime. So if you have a const variable inside a procedural for-loop, that variable could get initialized at every iteration during runtime. Because const variables get initialized at runtime, you can't use them where constant expressions are required by the compiler, like the size in a declaration. 

Parameter values can be overridden on a module instance by instance basis. And some tools even allow to override parameter values when you invoke simulation. You can’t do either using a macro.

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<div class="post-metadata">

**Author:** ![J\_M](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/j/e99b99/32.png) [@J\_M](https://verificationacademy.com/forums/u/J_M)\
**Post date:** [September 29, 2022, 1:27pm UTC](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527/4 "2022-09-29T13:27:29Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527/3):_

Hi Dave, can you help me with this ?

```verilog

module top_driver #(parameter START_LANE = 0)

`define LANE_ID(lane_no)\
lane_drv u_lane``lane_no``_drv ()

`LANE_ID(0 + START_LANE) // 0 + parameter set for START_LANE when top_driver instantiated 
`LANE_ID(1 + START_LANE)
`LANE_ID(2 + START_LANE)
`LANE_ID(3 + START_LANE)
endmodule

```

it is giving me compile error as parameter and `define can not work together

error - u\_lane0 + START\_LANE\_drv // creating instance like this

what I want is, whatever LANE number I give when top\_driver is instantiated lane\_driver should start from that

example if START\_LANE is 0, my lane driver should look like this,  
u\_lane0\_drv()  
u\_lane1\_drv()  
u\_lane2\_drv()  
u\_lane3\_drv()

and if START\_LANE is 4, my lane driver should be,  
u\_lane4\_drv()  
u\_lane5\_drv()  
u\_lane6\_drv()  
u\_lane7\_drv()

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<div class="post-metadata">

**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [September 29, 2022, 2:54pm UTC](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527/5 "2022-09-29T14:54:42Z")

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_In reply to [J\_M](https://verificationacademy.com/forums/t/define-vs-parameter-difference/37527/4):_

Macros _ARE_ just text substitutions. They have no knowledge of SystemVerilog syntax and just pass the argument text through.

What you might want to use is a generate-for loop

```verilog
module top_driver #(parameter START_LANE = 0)
 
for (genvar i = START_LANE; i<START_LANE+4;i++ begin : lane
     lane_drv u ()

endmodule

```

This creates instance names lane[0].u, lane[1].u, lane[2].u, and lane[3].u. See section 27.4 Loop generate constructs in the [IEEE 1800-2017 SystemVerilog LRM](https://ieeexplore.ieee.org/document/8299595).