# Default sequence

**URL:** <https://verificationacademy.com/forums/t/default-sequence/33172>\
**Category:** UVM\
**Tags:** UVM\
**Created:** [June 2, 2017, 10:20am UTC](https://verificationacademy.com/forums/t/default-sequence/33172 "2017-06-02T10:20:53Z")\
**Posts on this page:** 8\
**Page:** 1

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**Author:** ![piyushpatel123](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/e19b73/32.png) [@piyushpatel123](https://verificationacademy.com/forums/u/piyushpatel123)\
**Post date:** [June 2, 2017, 10:20am UTC](https://verificationacademy.com/forums/t/default-sequence/33172/1 "2017-06-02T10:20:53Z")

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1. We can set default sequence in uvm test using “config\_db::set” but in which component “config\_db::get” method is declare?

2. How object of the default sequence is created as there is no start method in testcase? like,

Thanks

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**Author:** ![cgales](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/c/ccd318/32.png) [@cgales](https://verificationacademy.com/forums/u/cgales)\
**Post date:** [June 2, 2017, 11:26am UTC](https://verificationacademy.com/forums/t/default-sequence/33172/2 "2017-06-02T11:26:19Z")

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_In reply to [piyushpatel123](https://verificationacademy.com/forums/t/default-sequence/33172):_

Starting a sequence using ‘default\_sequence’ is a legacy method carried over from OVM and is not recommended. You should explicitly .start() all of your sequences in your test.

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**Author:** ![piyushpatel123](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/e19b73/32.png) [@piyushpatel123](https://verificationacademy.com/forums/u/piyushpatel123)\
**Post date:** [June 2, 2017, 11:35am UTC](https://verificationacademy.com/forums/t/default-sequence/33172/3 "2017-06-02T11:35:32Z")

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_In reply to [cgales](https://verificationacademy.com/forums/t/default-sequence/33172/2):_

Thanks cgales for your reply but i just want to know how it is working.

Thanks

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**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [June 2, 2017, 12:05pm UTC](https://verificationacademy.com/forums/t/default-sequence/33172/4 "2017-06-02T12:05:40Z")

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_In reply to [piyushpatel123](https://verificationacademy.com/forums/t/default-sequence/33172/3):_

Using the Default sequence Approach the sequence is started automatically. You don’t have to perform get on the uvm\_config\_db.  
In contrast to the OVM you have to set the default\_sequence on the run\_phase of the sequence under consideration like this:

```verilog

class my_test extends uvm_test;
  function void build_phase(uvm_phase phase);
    uvm_config_db#(uvm_object_wrapper)::set(null, "/.*sequencer.run_phase/",
              "default_sequence", my_sequence::get_type() );
    ....
  endfunction

```

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<div class="post-metadata">

**Author:** ![piyushpatel123](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/p/e19b73/32.png) [@piyushpatel123](https://verificationacademy.com/forums/u/piyushpatel123)\
**Post date:** [June 3, 2017, 2:35pm UTC](https://verificationacademy.com/forums/t/default-sequence/33172/5 "2017-06-03T14:35:51Z")

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_In reply to [chr\_sue](https://verificationacademy.com/forums/t/default-sequence/33172/4):_

Thanks for your reply. I also know the same but I want to know the full mechanism that how it is working?

Thanks

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<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [June 3, 2017, 3:03pm UTC](https://verificationacademy.com/forums/t/default-sequence/33172/6 "2017-06-03T15:03:00Z")

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_In reply to [piyushpatel123](https://verificationacademy.com/forums/t/default-sequence/33172/5):_  
For more Details see The UVM User Guide (1.1d)  
3.10.3 Configuring the Sequencer’s Default Sequence  
Note main\_phase is one of the sub-phases of the run\_phase. In this Phase the simulations takes place.

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**Author:** ![radheyshamloya](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/d78d45/32.png) [@radheyshamloya](https://verificationacademy.com/forums/u/radheyshamloya)\
**Post date:** [February 9, 2018, 6:30am UTC](https://verificationacademy.com/forums/t/default-sequence/33172/7 "2018-02-09T06:30:47Z")

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_In reply to [chr\_sue](https://verificationacademy.com/forums/t/default-sequence/33172/6):_

do we need to define run phase in sequencer?

Thank you

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<div class="post-metadata">

**Author:** ![chr\_sue](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/chr_sue/32/1199_2.png) [@chr\_sue](https://verificationacademy.com/forums/u/chr_sue)\
**Post date:** [February 9, 2018, 7:56am UTC](https://verificationacademy.com/forums/t/default-sequence/33172/8 "2018-02-09T07:56:49Z")

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_In reply to [ASICverif](https://verificationacademy.com/forums/t/default-sequence/33172/7):_

Normally you do not need to define the run\_phase in your sequencer, if you do not want to do very specific things.