# Covergroup with sampling event

**URL:** <https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171>\
**Category:** Coverage\
**Tags:** covergroup, SystemVerilog, Coverage\
**Created:** [January 13, 2023, 6:55am UTC](https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171 "2023-01-13T06:55:34Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![SUNODH](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/sunodh/32/4411_2.png) [@SUNODH](https://verificationacademy.com/forums/u/SUNODH)\
**Post date:** [January 13, 2023, 6:55am UTC](https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171/1 "2023-01-13T06:55:34Z")

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Hi ,

I have tried to sample the cover group by having a sample event @(posedge clk) it was showing errors like

```verilog

Error-[SNACGWC] Illegal sample call for covergroup
testbench.sv, 28
func_coverage, "c_group"
  Covergroup having sampling event is not allowed to be sampled using the 
  predefined task 'sample'.

```

I just used a basic example below  
[edaplayground](https://www.edaplayground.com/x/RUuu)

So can I know why we can’t use a sample event for covergroup for sampling  
Are they is any way we can sample even using the event ?

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [January 13, 2023, 8:05am UTC](https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171/2 "2023-01-13T08:05:10Z")

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_In reply to [SUNODH](https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171):_

Although not a good practice, there is nothing illegal about declaring a sampling event and calling the sample method. Try a different tool.

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<div class="post-metadata">

**Author:** ![SUNODH](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/sunodh/32/4411_2.png) [@SUNODH](https://verificationacademy.com/forums/u/SUNODH)\
**Post date:** [January 13, 2023, 9:14am UTC](https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171/3 "2023-01-13T09:14:00Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171/2):_

Hi dave\_59 ,

You said it was not a good practice can I know why it was not?

and working for other tools thank you for your help.

Thanks & Regards  
Sunodh

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<div class="post-metadata">

**Author:** ![Have\_A\_Doubt](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/h/51bf81/32.png) [@Have\_A\_Doubt](https://verificationacademy.com/forums/u/Have_A_Doubt)\
**Post date:** [January 13, 2023, 2:44pm UTC](https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171/4 "2023-01-13T14:44:46Z")

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_In reply to [SUNODH](https://verificationacademy.com/forums/t/covergroup-with-sampling-event/41171/3):_

> You said it was not a good practice can I know why it was not?

In your code you have mentioned the sampling event already ::

```verilog

 covergroup c_group @( posedge clk ); // Samples automatically on each posedge of clk 
   .......

```

Since the sampling is done automatically there is no need for user to call sample() .
