# Combinationally sampling an input in clocking block

**URL:** <https://verificationacademy.com/forums/t/combinationally-sampling-an-input-in-clocking-block/33245>\
**Category:** SystemVerilog\
**Tags:** clocking-block-testbench, SystemVerilog\
**Created:** [June 24, 2017, 12:59am UTC](https://verificationacademy.com/forums/t/combinationally-sampling-an-input-in-clocking-block/33245 "2017-06-24T00:59:50Z")\
**Posts on this page:** 1\
**Showing post:** 6

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**Author:** ![bitfiddler0](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/b/ebca7d/32.png) [@bitfiddler0](https://verificationacademy.com/forums/u/bitfiddler0)\
**Post date:** [June 24, 2017, 8:37am UTC](https://verificationacademy.com/forums/t/combinationally-sampling-an-input-in-clocking-block/33245/6 "2017-06-24T08:37:40Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/combinationally-sampling-an-input-in-clocking-block/33245/5):_

Thanks for the info. Can you comment on how I can get the behavior I want? (asserting wren in the same cycle as ready)

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