# Bitwise and of array,array reduction operator

**URL:** <https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [December 25, 2016, 4:00pm UTC](https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687 "2016-12-25T16:00:29Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![abhijain](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/f6c823/32.png) [@abhijain](https://verificationacademy.com/forums/u/abhijain)\
**Post date:** [December 25, 2016, 4:00pm UTC](https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687/1 "2016-12-25T16:00:29Z")

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i am trying to assing bitwise and of array to single bit wire

```verilog
 wire [3:0] mpu_region_vr0 = `MPU_PATH.mpu_region_v_r;///rtl path
 wire mpu_region_vr =mpu_region_vr0[0] & 
                                      mpu_region_vr0[1] & 
                                      mpu_region_vr0[2] & 
                                      mpu_region_vr0[3] ;

```

i tried with the function .and() as well still am getting same error is it tool related issue?

i am getting  
Incompatible unpacked dimensions in assignment  
Arrays with incompatible unpacked dimensions cannot be used in assignments,  
initializations and instantiations.

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [December 25, 2016, 4:13pm UTC](https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687/2 "2016-12-25T16:13:45Z")

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_In reply to [abhineet2210](https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687):_  
There are no unpacked dimensions in what you have shown. What is the declaration for _mpu\_region\_v\_r_?

This should have worked:

```verilog
wire mpu_region_vr = &mpu_region_vr0;

```

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<div class="post-metadata">

**Author:** ![abhijain](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/f6c823/32.png) [@abhijain](https://verificationacademy.com/forums/u/abhijain)\
**Post date:** [December 25, 2016, 4:34pm UTC](https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687/3 "2016-12-25T16:34:48Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687/2):_

reg mpu\_region\_v\_r [`REGION\_RANGE];

still getting the same error

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<div class="post-metadata">

**Author:** ![sbellock](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/f4b2a3/32.png) [@sbellock](https://verificationacademy.com/forums/u/sbellock)\
**Post date:** [December 27, 2016, 5:29am UTC](https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687/4 "2016-12-27T05:29:01Z")

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_In reply to [abhineet2210](https://verificationacademy.com/forums/t/bitwise-and-of-array-array-reduction-operator/32687/3):_

mpu\_region\_v\_r is an unpacked array that you are trying to assign to mpu\_region\_vr0, which is a packed array. If the bits line up you can use the streaming operator for unpacked-to-packed array conversion.

```verilog
wire [3:0] mpu_region_vr0 = {<<{`MPU_PATH.mpu_region_v_r}};

```