Bind a vhdl entity to a uvm class

SystemVerilog
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2

In reply to shaygueta:

You can bind a module that has a class object into a VHDL entity. The following examples bind into a Verilog module, but also work the same for binding into a VHDL entity.

https://verificationacademy.com/cookbook/connect/twokingdomsfactory
https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection