# Backdoor Register Layer Access

**URL:** <https://verificationacademy.com/forums/t/backdoor-register-layer-access/34398>\
**Category:** UVM\
**Tags:** register-backdoor-access-on-VHDL-DUT, UVM, SystemVerilog, registerlayer\
**Created:** [April 26, 2018, 4:36pm UTC](https://verificationacademy.com/forums/t/backdoor-register-layer-access/34398 "2018-04-26T16:36:28Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![Sanjin\_Arsenovic](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/a9a28c/32.png) [@Sanjin\_Arsenovic](https://verificationacademy.com/forums/u/Sanjin_Arsenovic)\
**Post date:** [April 26, 2018, 4:38pm UTC](https://verificationacademy.com/forums/t/backdoor-register-layer-access/34398/2 "2018-04-26T16:38:25Z")

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_In reply to [Sanjin\_Arsenovic](https://verificationacademy.com/forums/t/backdoor-register-layer-access/34398):_

sorry about indentations, i am not sure why are they missing i didnt post like this.

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