# Atomic net datatype question

**URL:** <https://verificationacademy.com/forums/t/atomic-net-datatype-question/35943>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog\
**Created:** [April 7, 2019, 11:47am UTC](https://verificationacademy.com/forums/t/atomic-net-datatype-question/35943 "2019-04-07T11:47:25Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![haithamx15](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/h/fbc32d/32.png) [@haithamx15](https://verificationacademy.com/forums/u/haithamx15)\
**Post date:** [April 7, 2019, 11:47am UTC](https://verificationacademy.com/forums/t/atomic-net-datatype-question/35943/1 "2019-04-07T11:47:25Z")

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Hello, in LRM (2012) 6.6.7 User-defined nettypes,

> An atomic net is a net whose value is updated and resolved as a whole. A net declared with a user-defined  
> nettype is an atomic net. Similarly, a logic net is an atomic net, but a logic vector net is not an atomic  
> net as each logic element is resolved and updated independently. While an atomic net may have a singular  
> or aggregate value, each atomic net is intended to describe a single connection point in the design.

I could not understand what LRM means by atomic net, or what does “updated and resolved as a whole mean”

Excuse my ignorance, thank you.

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [April 7, 2019, 3:22pm UTC](https://verificationacademy.com/forums/t/atomic-net-datatype-question/35943/2 "2019-04-07T15:22:51Z")

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_In reply to [haithamx15](https://verificationacademy.com/forums/t/atomic-net-datatype-question/35943):_

I’m going to use the term “bit” here to mean the bit width of the 4-state **logic** data type, not to be confused with the SystemVerilog 2-state **bit** data type.

The built-in wire nettype can be a single bit(scalar), or many bits packed into an array (vector). Nets can have multiple drivers(continuous assignments), but each bit of vector gets resolved independently using a truth table depending on the strength and built-in net type. For example, if a wire has a 1 and 0 driving a bit, the resolution of that bit is X. You can also select individual or a range of bits to read or drive.

The LRM is using the terminology **atomic** to describe the behavior of that scalar bit; meaning you cannot divide it into smaller pieces below a bit. User-defined nettyps are always atomic regardless of the underlying data type. You could have an 8-bit user-defined nettype where those 8-bits represent a voltage, and when there are multiple drivers, you could define the resolution to be the average value of all the drivers. It makes no sense in that case to look at the individual bits of that nettype.

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**Author:** ![haithamx15](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/h/fbc32d/32.png) [@haithamx15](https://verificationacademy.com/forums/u/haithamx15)\
**Post date:** [April 7, 2019, 5:04pm UTC](https://verificationacademy.com/forums/t/atomic-net-datatype-question/35943/3 "2019-04-07T17:04:36Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/atomic-net-datatype-question/35943/2):_

> _In reply to [haithamx15](https://verificationacademy.com/forums/t/atomic-net-datatype-question/35943/2):_  
> I’m going to use the term “bit” here to mean the bit width of the 4-state **logic** data type, not to be confused with the SystemVerilog 2-state **bit** data type.  
> The built-in wire nettype can be a single bit(scalar), or many bits packed into an array (vector). Nets can have multiple drivers(continuous assignments), but each bit of vector gets resolved independently using a truth table depending on the strength and built-in net type. For example, if a wire has a 1 and 0 driving a bit, the resolution of that bit is X. You can also select individual or a range of bits to read or drive.  
> The LRM is using the terminology **atomic** to describe the behavior of that scalar bit; meaning you cannot divide it into smaller pieces below a bit. User-defined nettyps are always atomic regardless of the underlying data type. You could have an 8-bit user-defined nettype where those 8-bits represent a voltage, and when there are multiple drivers, you could define the resolution to be the average value of all the drivers. It makes no sense in that case to look at the individual bits of that nettype.

Crystal clear, thank you Dave.