I developed a UVM testbench. The design has two output. data and block_out. The algorithm which design selects to block_out reach 1 is differ from the predictor and block_out may becomes 1 sooner than design.
I wrote a scoreboard in this way: it collects predictor output transaction in a fifo. Wenever a design output transaction arrived in scoreboard, scoreboard compares it in that fifo. If it does not find any transaction in fifo, it states UVM_ERROR.
It was OK but there is a problems. The predictor may exit from block_lock sooner(after it was lock) and the design output sends transaction which the predictor has not generate this.
I don’t know how developed an scoreboard which number of transaction in predictor and design not the same!
Many things that impossible to understand to help you out:
What do you mean in “reach 1”?
“may becomes 1 sooner than design”?
What lock?
Is it internal DUT logic/feature?
Please add a block diagram of the DUT and few examples of possible inputs + outputs with timing.