Associative array declaration

SystemVerilog
2

In reply to UVM_learner6:

Looks like the LRM is a bit murky on that one. It states:

7.8.4 Integral index

For example:
  int array_name1 [ integer ];
  typedef bit signed [4:1] SNibble;
  int array_name2 [ SNibble ];
  typedef bit [4:1] UNibble;
  int array_name3 [ UNibble ];

So it looks like


typedef bit [5:0] my_type;
trans aa[my_type];

is legal.

But is your example illegal? I don’t think the LRM says yes or no for that one.