# Assigning a bit in SV Assertion

**URL:** <https://verificationacademy.com/forums/t/assigning-a-bit-in-sv-assertion/36810>\
**Category:** SystemVerilog\
**Tags:** Assertion-Based-Verification, assert-property, SystemVerilog, assertion\
**Created:** [November 16, 2019, 8:23am UTC](https://verificationacademy.com/forums/t/assigning-a-bit-in-sv-assertion/36810 "2019-11-16T08:23:54Z")\
**Posts on this page:** 1\
**Showing post:** 9

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**Author:** ![atanu.biswas](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/9de0a6/32.png) [@atanu.biswas](https://verificationacademy.com/forums/u/atanu.biswas)\
**Post date:** [November 18, 2019, 8:01am UTC](https://verificationacademy.com/forums/t/assigning-a-bit-in-sv-assertion/36810/9 "2019-11-18T08:01:39Z")

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_In reply to [ben@SystemVerilog.us](https://verificationacademy.com/forums/t/assigning-a-bit-in-sv-assertion/36810/8):_

Hi Ben,

I understood your point and I definitely agree with it. But the issue is that in my project there are multiple clock domains that are being used. There are internal registers that are written via the APB interface. There is one to one mapping of those registers with RTL’s output signals. The output is sampled at a clock which runs at a much higher frequency than that of the APB. So the issue is that if there is some glitch sampled by the RTL at that high frequency clock, I fear that the assertion wont be able to catch it. Hence to make it fool proof I am using the always\_comb block for the data check.

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