# $assertoff giving error during compilation

**URL:** <https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524>\
**Category:** SystemVerilog\
**Tags:** SVA, system-verilog-assertion, SystemVerilog, assertion\
**Created:** [November 10, 2016, 4:45am UTC](https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524 "2016-11-10T04:45:09Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![svishnu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/d2c977/32.png) [@svishnu](https://verificationacademy.com/forums/u/svishnu)\
**Post date:** [November 10, 2016, 4:45am UTC](https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524/1 "2016-11-10T04:45:09Z")

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I used $assertoff() to disable assertions in my rtl. But its giving this error **Only elaboration system tasks allowed here** while compiling. How to resolve this issue?

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**Author:** ![sharvil111](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/sharvil111/32/3790_2.png) [@sharvil111](https://verificationacademy.com/forums/u/sharvil111)\
**Post date:** [November 10, 2016, 5:23am UTC](https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524/2 "2016-11-10T05:23:14Z")

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_In reply to [vishnu\_intel](https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524):_

Can you show some part of code? Or some pseudo-code that gives the above error?

I guess that you are using $assertoff in wrong place. $assertoff must be used in some **procedural blocks** like initial/always blocks.

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**Author:** ![svishnu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/s/d2c977/32.png) [@svishnu](https://verificationacademy.com/forums/u/svishnu)\
**Post date:** [November 10, 2016, 5:41am UTC](https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524/3 "2016-11-10T05:41:45Z")

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_In reply to [sharvil111](https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524/2):_

```verilog

module top;
  reg clk;
  reg [2:00]d;
  reg b ,c;

  initial begin
    clk=0;
d=0;
#5 d=1;
#2 d=2;
#4 d=3; 
#50 $finish;
  end
  always #4 clk=!clk;

**$assertoff();**
property d_stability;
@(posedge clk)
!$stable(d) |=> $stable(d) [*2];
endproperty : d_stability

assert property(d_stability);
endmodule

```

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<div class="post-metadata">

**Author:** ![sharvil111](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/sharvil111/32/3790_2.png) [@sharvil111](https://verificationacademy.com/forums/u/sharvil111)\
**Post date:** [November 10, 2016, 5:54am UTC](https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524/4 "2016-11-10T05:54:03Z")

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_In reply to [vishnu\_intel](https://verificationacademy.com/forums/t/assertoff-giving-error-during-compilation/32524/3):_

As I mentioned, **$assertoff needs to be in procedural block**. Just add _initial begin…end_ before $assertoff.

```verilog
initial begin
$assertoff();
end

```