# Assertions

**URL:** <https://verificationacademy.com/forums/t/assertions/33048>\
**Category:** Coverage\
**Tags:** Coverage, Cookbook-CoverageUART-Example-Test-Plan\
**Created:** [April 17, 2017, 9:40am UTC](https://verificationacademy.com/forums/t/assertions/33048 "2017-04-17T09:40:30Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![vikram\_kolanu](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/v/d07c76/32.png) [@vikram\_kolanu](https://verificationacademy.com/forums/u/vikram_kolanu)\
**Post date:** [April 17, 2017, 9:40am UTC](https://verificationacademy.com/forums/t/assertions/33048/1 "2017-04-17T09:40:30Z")

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i have a basic doubt of to what signals assertions are necessary in a design.  
Example: can we write assertions for the registers ? or for the bits representing some status and interrupt flag in the register.  
i am unable to differentiate what comes to coverage and what comes to assertions .

please help in in this basic idea

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<div class="post-metadata">

**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [April 17, 2017, 6:10pm UTC](https://verificationacademy.com/forums/t/assertions/33048/2 "2017-04-17T18:10:37Z")

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_In reply to [vikram kolanu](https://verificationacademy.com/forums/t/assertions/33048):_

> … what signals assertions are necessary in a design.

Looking at assertions in terms of “signals” is the wrong way to use assertions. Instead, assertions should be seen in terms of **properties** and **requirements**. The _signals_ are the byproducts that are used to identify and clarify the requirements.  
So, what are the properties and requirements of a design? Where do they come from?  
They come from detailed specs about the design, architectural plans, standard interface docs, etc.  
SVA concurrent assertions are based on clocks, thus signals off registers will typically be used, but so do signals off of ports. You addressed “interrupt flags”, sure, they are included in an assertion for requirements such as _Upon receipt of a message, an interrupt shall be generated. That interrupt needs to be acknowledged within 5 cycles._

```verilog

default clocking @(posedge clk); endclocking
ap_uart_eot: assert property(@(posedge uart_clk) uart_eot |-> @(posedge clk) uart_interrupt);  
ap_intrpt2ack: assert property(uart_interrupt |-> ##[1:5] intrpt_ack);   

```

## From my [SVA Handbook](http://goo.gl/JOfuEB) see how assertions can also be used in a requirement document: [http://systemverilog.us/req\_verif\_plan.pdf](http://systemverilog.us/req_verif_plan.pdf)

Ben Cohen  
[http://www.systemverilog.us/](http://www.systemverilog.us/) [ben@systemverilog.us](mailto:ben@systemverilog.us)  
For training, consulting, services: contact [http://cvcblr.com/home](http://cvcblr.com/home)

- [SVA Handbook 4th Edition, 2016 ISBN 978-1518681448](http://goo.gl/JOfuEB)
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- [Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712](https://goo.gl/d10QHh)
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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