# Assertion Problem

**URL:** <https://verificationacademy.com/forums/t/assertion-problem/39143>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, assertion\
**Created:** [June 3, 2021, 6:50pm UTC](https://verificationacademy.com/forums/t/assertion-problem/39143 "2021-06-03T18:50:39Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![Abhishek405](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/9fc348/32.png) [@Abhishek405](https://verificationacademy.com/forums/u/Abhishek405)\
**Post date:** [June 3, 2021, 10:19pm UTC](https://verificationacademy.com/forums/t/assertion-problem/39143/3 "2021-06-03T22:19:30Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/assertion-problem/39143/2):_

Hi Dave,

This is the requirement: A rises only once after B rises; until B rises again

Also, A & B are synchronous to a clock.

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