# Assertion Problem

**URL:** <https://verificationacademy.com/forums/t/assertion-problem/39143>\
**Category:** SystemVerilog\
**Tags:** SystemVerilog, assertion\
**Created:** [June 3, 2021, 6:50pm UTC](https://verificationacademy.com/forums/t/assertion-problem/39143 "2021-06-03T18:50:39Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![Abhishek405](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/9fc348/32.png) [@Abhishek405](https://verificationacademy.com/forums/u/Abhishek405)\
**Post date:** [June 3, 2021, 6:50pm UTC](https://verificationacademy.com/forums/t/assertion-problem/39143/1 "2021-06-03T18:50:39Z")

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What would be the right assertion to capture this behavior → signal A (level or pulse) rises only once after signal B(pulse)?

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [June 3, 2021, 10:08pm UTC](https://verificationacademy.com/forums/t/assertion-problem/39143/2 "2021-06-03T22:08:52Z")

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_In reply to [letzask](https://verificationacademy.com/forums/t/assertion-problem/39143):_

A few questions:

Do you mean to say A rises only once after B rises; until B rises again, or A must never rise again?  
Are A and B synchronous to a clock or asynchronous?

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**Author:** ![Abhishek405](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/a/9fc348/32.png) [@Abhishek405](https://verificationacademy.com/forums/u/Abhishek405)\
**Post date:** [June 3, 2021, 10:19pm UTC](https://verificationacademy.com/forums/t/assertion-problem/39143/3 "2021-06-03T22:19:30Z")

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_In reply to [dave\_59](https://verificationacademy.com/forums/t/assertion-problem/39143/2):_

Hi Dave,

This is the requirement: A rises only once after B rises; until B rises again

Also, A & B are synchronous to a clock.

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**Author:** ![dave\_59](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/dave_59/32/4499_2.png) [@dave\_59](https://verificationacademy.com/forums/u/dave_59)\
**Post date:** [June 4, 2021, 3:40am UTC](https://verificationacademy.com/forums/t/assertion-problem/39143/4 "2021-06-04T03:40:16Z")

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_In reply to [letzask](https://verificationacademy.com/forums/t/assertion-problem/39143/3):_

I believe this is the same requirement: [how to write the assertion that between two requests grant should be there | Verification Academy](https://verificationacademy.com/forums/systemverilog/how-write-assertion-between-two-requests-grant-should-be-there#reply-98094)