# Assertion Failing Because Signals Set to 'X'

**URL:** <https://verificationacademy.com/forums/t/assertion-failing-because-signals-set-to-x/33240>\
**Category:** Coverage\
**Tags:** SystemVerilog, Assertion-system-verilog, Coverage, assertion-coverage\
**Created:** [June 22, 2017, 4:07pm UTC](https://verificationacademy.com/forums/t/assertion-failing-because-signals-set-to-x/33240 "2017-06-22T16:07:48Z")\
**Posts on this page:** 1\
**Showing post:** 5

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**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\
**Post date:** [June 24, 2017, 1:25am UTC](https://verificationacademy.com/forums/t/assertion-failing-because-signals-set-to-x/33240/5 "2017-06-24T01:25:52Z")

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_In reply to [MayurKubavat](https://verificationacademy.com/forums/t/assertion-failing-because-signals-set-to-x/33240/4):_  
Thanks for correcting my code. Shows you why assertions should be reviewed.  
We’re human… and we make mistakes. In tis case, I meant to use the $past/  
Ben

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