# Assertion Failing Because Signals Set to 'X'

**URL:** <https://verificationacademy.com/forums/t/assertion-failing-because-signals-set-to-x/33240>\
**Category:** Coverage\
**Tags:** SystemVerilog, Assertion-system-verilog, Coverage, assertion-coverage\
**Created:** [June 22, 2017, 4:07pm UTC](https://verificationacademy.com/forums/t/assertion-failing-because-signals-set-to-x/33240 "2017-06-22T16:07:48Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![rachel.greenlee](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/r/b19c9b/32.png) [@rachel.greenlee](https://verificationacademy.com/forums/u/rachel.greenlee)\
**Post date:** [June 23, 2017, 6:17pm UTC](https://verificationacademy.com/forums/t/assertion-failing-because-signals-set-to-x/33240/4 "2017-06-23T18:17:23Z")

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Thanks for the replies. I played around with this for a bit and the solution that ended up working was using $isunknown (which I did not know about at the time).

```verilog

disable iff(reset) (!(counter[i] != 12'b0 && i_enable_cntrs == 1'b0) || $isunknown(counter[i])[*11]);

```

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