# ASSERTION: detects if one input is a delayed version of the other **URL:** \ **Category:** SystemVerilog\ **Tags:** SVA, SystemVerilog, Assertion-system-verilog\ **Created:** [June 25, 2020, 8:11am UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763 "2020-06-25T08:11:17Z")\ **Posts on this page:** 8\ **Page:** 1
**Author:** ![gumpena](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/g/ec9cab/32.png) [@gumpena](https://verificationacademy.com/forums/u/gumpena)\ **Post date:** [June 25, 2020, 8:11am UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/1 "2020-06-25T08:11:17Z")
Hi, I am new to SVA’s though I have written few assertions but found this one to be a little tricky. Please excuse me in case its a simple assertion. ![](https://verificationacademy.com/forums/uploads/default/original/1X/2902d3076e9b0fb46478a5717667d69d653950d4.jpeg) Please check the above image for the requirement: only 1 pass scenario exists since signal\_2 is expected to be exactly same as signal\_1 but a delayed version; fail (there can be many other fail scenarios in the picture i just mentioned 1 such case). Thanks in advance ---
**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\ **Post date:** [June 25, 2020, 9:39pm UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/2 "2020-06-25T21:39:17Z")
_In reply to [gumpena@usc.edu](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763):_ Keep in mind that an assertion is a statement or directive that a given property is required to hold. Assertions can be expressed in many ways, including regular code. In SystemVerilog, that can be done in SVA or other plain SystemVerilog options. Your requirement to verify that a wave of any shape, the duration of highs and lows of s1 are the same as s2, but delayed. It’s too complex to do in SVA, but you can use the task method, as explained in my paper SVA Alternative for Complex Assertions [https://verificationacademy.com/news/verification-horizons-march-2018-issue](https://verificationacademy.com/news/verification-horizons-march-2018-issue) Below is an untested method where I measure that the duration in cycles of s1 pulse in high level is the same as s2 (delayed) also staying a 1 for that duration. You need to do the same for when the signals are in the low state, the t\_fell() task. ```verilog task automatic t_rise(); int s1_r1r1; // S1 rise to rise int s2_r1r1; // S2 rise to rise s1_r1r1=0; fork begin // record wave for s1 while (s1==1) begin @(posedge clk) s1_r1r1++; // compute #cycles s1==1 end end begin while (s2==1) @(posedge clk); // wait for s2 to rise s2_r1r1=0; while (s2==1) begin @(posedge clk) s2_r1r1++; // compute #cycles s1==1 end end join label: assert (s1_r1r1==s2_r1r1) else $error("s1 high pulse != s2 high pulse "); endtask always @(posedge clk) begin if($rose(s1)) t_rise(); if($fell(s1)) t_fell(); end ``` Ben Cohen [http://www.systemverilog.us/](http://www.systemverilog.us/) [ben@systemverilog.us](mailto:ben@systemverilog.us) For training, consulting, services: contact [Home - My cvcblr](http://cvcblr.com/home) - SVA Handbook 4th Edition, 2016 ISBN 978-1518681448 - A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 - Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0 - Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712 - Component Design by Example ", 2001 ISBN 0-9705394-0-1 - VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1 - VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115 * * * 1. SVA Alternative for Complex Assertions [Verification Horizons - March 2018 Issue | Verification Academy](https://verificationacademy.com/news/verification-horizons-march-2018-issue) 2. [SVA: Package for dynamic and range delays and repeats | Verification Academy](https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats) 3. SVA in a UVM Class-based Environment [SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy](https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment) 4. [FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy](https://verificationacademy.com/forums/announcements/free-book-component-design-example-%E2%80%A6-step-step-process-using-vhdl-uart-vehicle) ---
**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\ **Post date:** [June 26, 2020, 5:56am UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/3 "2020-06-26T05:56:00Z")
_In reply to [ben@SystemVerilog.us](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/2):_ Another approach is to first compute the initial delay between S1 and S2 and store that in a variable. Using the package sva\_delay\_repeat\_range\_pkg; (item 2 in my signature). ```verilog // v is first computed. Assertions disabled $rose(S1) |-> q_dynamic_delay(v) ##0 $rose(S2); $fell(S1) |-> q_dynamic_delay(v) ##0 $fell(S2); ``` Ben Cohen [http://www.systemverilog.us/](http://www.systemverilog.us/) [ben@systemverilog.us](mailto:ben@systemverilog.us) For training, consulting, services: contact [Home - My cvcblr](http://cvcblr.com/home) - SVA Handbook 4th Edition, 2016 ISBN 978-1518681448 - A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 - Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0 - Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712 - Component Design by Example ", 2001 ISBN 0-9705394-0-1 - VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1 - VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115 * * * 1. SVA Alternative for Complex Assertions [Verification Horizons - March 2018 Issue | Verification Academy](https://verificationacademy.com/news/verification-horizons-march-2018-issue) 2. [SVA: Package for dynamic and range delays and repeats | Verification Academy](https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats) 3. SVA in a UVM Class-based Environment [SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy](https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment) 4). [FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy](https://verificationacademy.com/forums/announcements/free-book-component-design-example-%E2%80%A6-step-step-process-using-vhdl-uart-vehicle) ---
**Author:** ![gumpena](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/g/ec9cab/32.png) [@gumpena](https://verificationacademy.com/forums/u/gumpena)\ **Post date:** [June 26, 2020, 7:37am UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/4 "2020-06-26T07:37:07Z")
Hi Ben, Thanks a ton for your prompt response, after going through the 2 solutions you mentioned above I came up with the below 2 scenarios (image attached: if not able to view here is the link [Imgur: The magic of the Internet](https://imgur.com/a/RJOUWgZ)). ![](https://imgur.com/a/RJOUWgZ) Though I have not tested the 2 approaches you mentioned. I suspect case 1 will return pseudo pass with approach 1 and case 2 is interesting to try with approach 2. However thanks a lot i can build upon the idea you gave and give this a try. ---
**Author:** ![user49](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user49/32/1084_2.png) [@user49](https://verificationacademy.com/forums/u/user49)\ **Post date:** [June 26, 2020, 4:01pm UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/5 "2020-06-26T16:01:00Z")
_In reply to [gumpena@usc.edu](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/4):_ Need to add ```verilog initial begin @(posedge clk); while (!rose(S1) || !$fell(S1)) begin assert(!rose(S2) || !$fell(S2)) else $error("S1 pulse wih no s2 pulse "); @(posedge clk); end end ``` Ben [systemverilog.us](http://systemverilog.us) ---
**Author:** ![user60](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user60/32/1096_2.png) [@user60](https://verificationacademy.com/forums/u/user60)\ **Post date:** [June 27, 2020, 7:52pm UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/6 "2020-06-27T19:52:20Z")
_In reply to [gumpena@usc.edu](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/5):_ Is your delay between sig1 and sig2 constant? If so, how about: ```verilog $rose(sig_2) |=> $past(sig_1, 3) ``` Similarly for $fell - also you may need to tweak the delays a bit (I didn’t test it). Good Luck Srini [www.verifworks.com](http://www.verifworks.com) ---
**Author:** ![gumpena](https://verificationacademy.com/forums/letter_avatar_proxy/v4/letter/g/ec9cab/32.png) [@gumpena](https://verificationacademy.com/forums/u/gumpena)\ **Post date:** [June 28, 2020, 1:15am UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/7 "2020-06-28T01:15:51Z")
Thanks Ben for the Solution, @Srini The delay is not constant that is the reason I could not think of any SVA. ---
**Author:** ![user60](https://verificationacademy.com/forums/user_avatar/verificationacademy.com/user60/32/1096_2.png) [@user60](https://verificationacademy.com/forums/u/user60)\ **Post date:** [June 28, 2020, 7:56pm UTC](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/8 "2020-06-28T19:56:45Z")
_In reply to [gumpena@usc.edu](https://verificationacademy.com/forums/t/assertion-detects-if-one-input-is-a-delayed-version-of-the-other/37763/7):_ You can get a partial check through some modeling code: ```verilog bit s1_seen; always_ff @(posedge clk) begin : glue_logic if ($rose(sig_1) begin s1_seen <= 1'b1; end if ($rose(sig_2) begin s1_seen <= 1'b0; end end : glue_logic // Now a property.. $rose(sig_2) |-> s1_seen; ``` I term this as weak as it does not take care of all scenarios, but towards that direction. HTH Srini