Hi Abhishek,
You can use associative arrays, which are a part of the SystemVerilog IEEE 1800 standard. Associative arrays do not allocate storage until they are implemented and implement a lookup table for the elements of their declared type, so they are ideal for implemening non-contiguous elements of storage.
You can find more information about the implemention of associative arrays along with examples in the SystemVerilog Reference document in cdnshelp (or the direct location to the document is under ncroot/doc/sysverilog/ )
FWIW, some simulators support sparse arrays even inside design/Verilog code via pragma. IIRC Riviera (Aldec) and VCS supports it.
reg /*sparse*/ [31:0] sparsemem [0:1_048_575];
But with SV around, assoc-arrays are a good choice as it becomes sort of tool independent. But you still may require this trick with old, legacy code. Not sure if NC supports it though.